• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2009.05a
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• pp.360-363
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• 2009

Total monitoring device of leakage current in transformer can detects the flowing leakage current on the neutral line, and that is monitored at real-time by the transfer. If the over-flowing current is detected Total monitoring device of leakage current in transformer will warn the administrator to prevent electrical accident. In this thesis, we are going to explain about Total monitoring device of leakage current in transformer and the necessity of Total monitoring device of leakage current in transformer through real-accident cases and equipment condition in Korea.

• The Journal of Information Technology
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• v.7 no.2
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• pp.69-76
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• 2004

This paper presents the results of spectral analysis about waveforms and leakage current waveforms on contaminated silicon insulators under various environment conditions.(salt fog, clean fog, rain). The larger the leakage current during 200ms, the higher the power spectrum at 60Hz. If contaminated insulators suffers from high salt density fog, the leakage current occurs with high crest value intermittently, results in the low spectrum. Analysis of leakage current data showed that this electrical activity was characterized by transient arcing behavior contaminants are deposited on the insulator surface during salt fog tests. This provides a path for the leakage current to flow along the surface of the insulator. It is important to have an indication of the pollution accumulation in order to evaluate the test performance of a particular insulator. If the drop in surface resistivity is severe enough, then the leakage current may escalate into service interrupting flashover that degrade power quality.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.1997-2000
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• 1999

본 연구에서 제시하는 기공세라믹(Porous Ceramic)에 의한 누설전류 측정법은 기공 사이즈가 일정한 Open Pore Cell내에서 도전성 물질 및 이온화된 물질이 기공 사이에 침투되었을 때 외부에서 전계를 가하므로 써 이들 이온화 된 물질이 chain처럼 배열되어 전기적 병렬회로를 구성시켜 미세한 누설전류를 흐르게 한다. 이 누설전류법에 의한 도전성분 검출을 여러 환경 배출가스에 대한 모의실험을 실시한 결과 기공세라믹인 센서 자체의 누설전류는 가스 온도 150 ($^{\circ}C$) 이상에서 급격한 변화를 보이고 200($^{\circ}C$)에서 센서 자체의 전류치와 가스를 주입하였을 때의 전류치와는 상당한 격차를 두고 변화됨을 알 수 있었다. 그리고 공장연돌이나 자동차 배기관에서 방출되는 가스 중 HC, CO, NO, $CO_2$, $SO_2$, $N_2$ 등에 대한 센서 특성이 각각 달리 나타남을 알 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.266-267
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• 2011

질화갈륨(GaN)은 높은 전자이동도 및 높은 항복전계를 가지며 낮은 온저항으로 인하여 에너지효율이 우수하기 때문에 고출력 전력소자 분야에서 많은 관심을 받고 있다. GaN을 이용한 고출력 전력소자의 경우 상용화 수준에 근접할 만한 기술적 진보가 있었으나, 페르미 레벨 고정(Fermi-level pinning) 현상, 소자의 누설전류 등 아직 해결되어야 할 문제를 갖고 있다. 본 연구에서는 실리콘 기판 위에 성장된 GaN 에피탁시를 활용한 고출력 전력소자의 누설전류를 억제시키기 위해 오믹 접합 중 Au의 상호확산을 억제하는 중간층 금속(Mo or Ni)을 변화시켰으며 오믹 열처리 온도에 따른 특성을 비교 연구하였다. $Cl_2$와 $BCl_3$를 이용하여 0.6 ${\mu}m$ 깊이의 메사 구조가 활성영역을 형성하였고, Si 도핑된 n-GaN 위에 Ti/Al/Mo/Au (20/100/25/200 nm) 와 Ti/Al/Ni/Au (20/100/25/200 nm) 오믹 접합을 각각 설계, 제작하였다. 오믹 열처리시의 GaN 표면오염을 방지하기 위해 $SiO_2$ 희생층을 증착하였다. 오믹 접합 형성을 위해 각 750$^{\circ}C$, 800$^{\circ}C$, 850$^{\circ}C$에서 30초간 열처리를 진행 하였으며, 이후 6 : 1 BOE 용액으로 $SiO_2$ 희생층을 제거하였다. 750, 800, 850$^{\circ}C$에서 Ti/Al/Mo/Au 구조의 오믹 접합 저항은 각 2.56, 2.34, 2.22 ${\Omega}$-mm 이었으며, Ti/Al/Ni/Au 구조의 오믹 접합 저항은 각 43.72, 2.64, 1.86 ${\Omega}$-mm이었다. Isolation 누설전류를 측정하기 위해서 두 개의 오믹 접합 사이에 메사 구조가 있는 테스트 구조를 제안하였다. Isolation 누설전류는 Ti/Al/Mo/Au 구조에서 두 오믹 접합 사이의 거리가 25 ${\mu}m$이고 100 V일 때 750, 800, 850 $^{\circ}C$의 열처리 온도에서 각 1.25 nA/${\mu}m$, 2.48 nA/${\mu}m$, 8.76 nA/${\mu}m$이었으며, Ti/Al/Ni/Au 구조에서는 각 1.58 nA/${\mu}m$, 2.13 nA/${\mu}m$, 96.36 nA/${\mu}m$이었다. 열처리 온도가 증가하며 오믹 접합 저항은 감소하였으나 isolation 누설전류는 증가하였다. 750$^{\circ}C$ 열처리에서 오믹 접합 저항은Ti/Al/Mo/Au 구조가 Ti/Al/Ni/Au 구조보다 약 17배 우수하였고, 850$^{\circ}C$ 고온의 열처리 경우 Ti/Al/Mo/Au 구조의 isolation 누설전류는 8.76 nA/${\mu}m$로 Ti/Al/Ni/Au의 누설전류 96.36 nA/${\mu}m$보다 약 11배 우수하였다. Ti/Al/Mo/Au가 Ti/Al/Ni/Au 보다 오믹 접합 저항과 isolation 누설전류 측면에서 전력용 GaN 소자에 적합함을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.335-340
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• 2002

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4${\AA}$ and 814${\AA}$, which have the gate area $10^3cm^2$. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.535-537
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• 2004

최근의 멀티미디어 시스템 설계 (예: 휴대폰, PDA) 경향에서 전력 소모를 줄이는 연구가 매우 긴요한 상황에, 본 연구는 누설 전류(leakage power)를 줄이는 연산 회로 아키텍쳐 합성 기법을 제안한다. 누설 전류를 줄이기 위한 방법으로 본 연구는 Dual threshold Voltage (Dual-V$_{T}$) 기법을 적용한다. 기존의 연구에서는 회로 설계 단계 중 논리나 트랜지스터 수준에서DUal-V$_{T}$를 적용한 방법과는 달리, 보다 상위 단계인 회로의 아키텍쳐 합성 단계에서의 지연시간 제약 조건을 만족하는 범위에서 최소의 누설전류 소모를 위한 합성 기법을 제안한다 따라서, 지연 시간과 누설전류 간의 Trade-Off를 이용하여 설계 조건에 맞는 융통성 있는 설계 결과를 얻을 수 있는 장점을 제공한다. 본 연구는 케리-세이브 가산기 (Carry-Save Adder) 모듈의 생성 과정에 국한된 합성 알고리즘의 적용을 보이고 있지만, 일반적인 연산 모듈을 사용한 아키텍쳐 설계 과정에서도 본 알고리즘을 쉽게 변형, 적용할 수 있다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.285-291
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• 2013

In this paper, MOS-Capacitor and MOSFET devices with a Low Level Leakage Current of oxide thickness, channel width and length respectively were to investigate the reliability characterizations mechanism of ultra thin gate oxide films. These stress induced leakage current means leakage current caused by stress voltage. The low level leakage current in stress and transient current of thin silicon oxide films during and after low voltage has been studied from strss bias condition respectively. The stress channel currents through an oxide measured during application of constant gate voltage and the transient channel currents through the oxide measured after application of constant gate voltage. The study have been the determination of the physical processes taking place in the oxides during the low level leakage current in stress and transient current by stress bias and the use of the knowledge of the physical processes for driving operation reliability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.10-15
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• 2012

This letter proposes a low-leakage SRAM using power-gating and voltage-level control. The power-gating scheme significantly reduces leakage power by shutting off the power supply to blank memory cell blocks. The voltage-level control scheme saves leakage power by raising the ground line voltage of SRAM cells and word line decoders in data-stored memory cell blocks. A $4K{\times}8bit$ SRAM chip was fabricated using a 1.2V $0.13{\mu}m$ CMOS process. The leakage powers are $1.23{\sim}9.87{\mu}W$ and $1.23{\sim}3.01{\mu}W$ for 0~100% memory usage in active and sleep modes, respectively. During the sleep mode, the proposed SRAM consumes 12.5~30.5% leakage power compared to the conventional SRAM.

• Journal of the Korean Ceramic Society
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• v.34 no.8
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• pp.803-810
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• 1997

Ba0.5Sr0.5TiO3 thin films were deposited by RF magnetron sputliring method in order to clarify the anneal condition and doping effect on loakage current Nb and Al were selected as electron donor and acceptor dopants respectively, in the BST films because they have been known to have nearly same ionic radii as Ti and thought to substitute Ti sites to influence the charge carrier and the acceptor state adjacent to the gram boundary. BST thin films prepared in-situ at elevated temperature showed selatively high leakage current density and low breakdown voltage. In order to achieve smooth surface and to improve electrical properties, BST thin films were deposited at room temperature and annealed at elevated temperature. Post-annealed BST thin films showed smoother surface morphology and lower leakage current density than in-situ prepared thin films. The leakage current density of Al doped thin films was measured to be around 10-8A/cm2, which is much lower than those of undoped and Nb doped BST films. The result clearly demonstrates that higher Schottky barrier and lower mobile charge carrier concentration achieved by annealing in the oxygen atmosphere and by Al doping are desirable for reducing leakage current density in BST thin films.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.3
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• pp.67-73
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• 2001

This paper resents a developed measuring device of resistive leakage current and a fundamental discussion of deterioration diagnosis for Zinc Oxide(ZnO) arrester blocks. We have developed the leakage current detection device for ageing test and durability evaluation for ZnO arrester blocks. The resistive leakage current can be used as an indicator to discriminate whether the ZnO arrester blocks is in good state or in bad. The resistive leakage current measuring system with the compensation circuit was designed and fabricated. The sauce tests for ZnO arrester blocks were investigated by observing the resistive leakage current together with fast Fourier transform analysis. The proposed monitoring systems for the resistive leakage current can effectively be used to investigate the electrophysical properties of ZnO arrester blocks in laboratory and to develop the techniques of forecasting the deterioration of ZnO arresters in electric power systems.