• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.4
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• pp.71-81
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• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.274-274
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• 2014

금속칼코게나이드 화합물중 하나인 $MoS_2$는 초저 마찰계수의 금속성 윤활제로 널리 사용되고 있으며 흑연과 비슷한 판상 구조를 지니고 있어 기계적 박리법을 통한 그래핀의 발견 이후 2차원 박막 합성법에 대한 활발한 연구가 진행되고 있다. 최근 다양한 응용이 진행 중인 그래핀의 경우 높은 전자이동도, 기계적 강도, 유연성, 열전도도 등 뛰어난 물리적 특성을 지니고 있으나 zero-bandgap으로 인한 낮은 on/off ratio는 thin film transistor (TFT), 논리회로(logic circuit) 등 반도체 소자 응용에 한계가 있다. 하지만 $MoS_2$는 벌크상태에서 약 1.2 eV의 indirect band-gap을 지닌 반면 단일층의 경우 1.8 eV의 direct-bandgap을 나타내고 있다. 또한 단일층 $MoS_2$를 이용하여 $HfO_2/MoS_2/SiO_2$ 구조의 트랜지스터를 제작하였을 때 $200cm^2/v^{-1}s^{-1}$의 높은 mobility와 $10^8$ 이상의 on/off ratio 나타낸다는 연구가 보고되어 있어 박막형 트랜지스터 응용을 위한 신소재로 주목을 받고 있다. 한편 2차원 $MoS_2$ 박막을 합성하기 위한 대표적인 방법인 기계적 박리법의 경우 고품질의 단일층 $MoS_2$ 성장이 가능하지만 대면적 합성에 한계를 지니고 있으며 화학기상증착법(CVD)의 경우 공정 gas의 분해를 위한 높은 온도가 요구되므로 박막형 투명 트랜지스터 응용을 위한 플라스틱 기판으로의 in-situ 성장이 어렵기 때문에 이를 보완할 수 있는 $MoS_2$ 박막 합성 공정 개발이 필요하다. 특히 Plasma enhanced chemical vapor deposition (PECVD) 방법은 공정 gas가 전기적 에너지로 분해되어 chamber 내부에서 cold-plasma 형태로 존 재하기 때문에 박막의 저온성장 및 대면적 합성이 가능하며 고진공을 바탕으로 합성 중 발생하는 오염 요소를 효과적으로 제어할 수 있다. 본 연구에서는PECVD를 이용하여 plasma power, 공정압력, 공정 gas의 유량 등 다양한 공정 변수를 조절함으로써 저온, 저압 조건하에서의 $MoS_2$ 박막 성장 가능성을 확인하였으며 전구체로는 Mo 금속과 $H_2S$ gas를 사용하였다. 또한 향후 flexible 소자 응용을 위한 플라스틱 기판의 녹는점을 고려하여 공정 온도는 $300^{\circ}C$ 이하로 설정하였으며 합성된 $MoS_2$ 박막의 두께 및 화학적 구성은 Raman spectroscopy를 이용하여 확인 하였다. 공정온도 $200^{\circ}C$와 $150^{\circ}C$에서 성장한 $MoS_2$ 박막의 Raman peak의 경우 상대적으로 낮은 공정온도로 인하여 Mo와 H2S의 화학적 결합이 감소된 것을 관찰할 수 있었고 $300^{\circ}C$의 경우 약 $26{\sim}27cm^{-1}$의 Raman peak 간격을 통해 5~6층의 $MoS_2$ 박막이 형성 된 것을 확인할 수 있었다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.123-131
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• 2002

In this paper, a new standard basis parallel ternary-valued multiplier circuit designed using current mode CMOS is presented. Prior to constructing the GF(3$^{ｍ}$) multiplier circuit, we provide a GF(3) adder and a GF(3) multiplier with truth tables and symbolize them, and also design them using current mode CMOS circuit. Using the basic ternary operation concept, a ternary adder and a multiplier, we develop the equations to multiply arbitrary two elements over GF(3$^{ｍ}$). Following these equations, we can design a multiplier generalized to GF(3$^{ｍ}$). For the proposed circuit in this paper, we show the example in GF(3$^{3}$). In this paper, we assemble the operation blocks into a complete GF(3$^{ｍ}$) multiplier. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer than other circuit. We verify the proposed circuit by functional simulation and show its result.

• Transactions of the KSME C: Technology and Education
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• v.4 no.1
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• pp.63-71
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• 2016

Although mechatronics education in a mechanical engineering curriculum is recently recognized as important, its experimental education has been done generally in the laboratory equipped with all the apparatus and could not be done at home by students. This paper introduces experimental educations on mechatronics, e.g., digital logic circuits, 7-segment LED drive, square wave generation, microcontroller programming using assembly and C languages, timer interrupt, and step motor drive using a small 5 V power supply, a breadboard, various electronic and electric components, a microcontroller and its programmer, a step motor, and a student's PC. In the developed mechatronics course, experimental educations are scheduled in parallel with content's lectures together, and cheap and economic experimental environment is prepared for students in which students can easily practice experimental works in advance or later at home by themselves.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1113-1119
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• 2013

In this letter, a new approach is proposed for the design of a multi antenna for MIMO wireless devices. The proposed antenna covers various LTE(Long Term Evolution) service bands: band 17(704~746 MHz), band 13(746~787 MHz), band 5(824~894 MHz), and band 8(880~960 MHz). The proposed main antenna consists of a conventional monopole antenna with an inverted L-shaped slit for wideband operation. The proposed the LTE sub antenna is based on a switch loaded loop antenna structure, with a resonance frequency that can be controlled by capacitance of a logic circuit. The tuning technique for the LTE Rx antenna uses a RF MEMS(Micro-Electro mechanical system) to match the impedances to realize the bands of interest. Because the two proposed antennas are polarized orthogonally to each other, the ECC(Envelope Correlation Coefficient) characteristic between two antennas was measured to be very low (below 0.06) with an isolation characteristic below -20 dB between the two antennas in the operating overall LTE bands. The proposed antenna is particularly attractive for mobile devices that integrate LTE multiple systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.56-65
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• 2006

The Quantum-dot Cellular Automata (QCA) can be considered as a candidate for the next generation digital logic implementation technology due to their small feature sizes and ultra low power consumption. Up to now, several designs using Uh technology have been proposed. However, we found not all of the designs function properly. Furthermore, no general design guidelines have been proposed so far. A straightforward extension of a simple functional design pattern may fail. This makes designing a large scale circuits using QCA technology an extremely time-consuming process. In this paper, we show several critical vulnerabilities related to unbalanced input paths to QCA gates and sneak noise paths in QCA interconnect structures. In order to make up the vulnerabilities, a disciplinary guideline will be proposed. Also, we present a fast adder which has been designed by the discipline, and verified to be functional by the simulation.