• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.451-451
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• 2013

현재 세계적으로 에너지 공급원의 다변화가 시급한 실정이며 그 후보로 태양에너지, 풍력 및 수력에너지와 같은 신재생 에너지에 대한 연구분야가 부각되고 있다. 전체 에너지 중 신재생 에너지의 비중은 빠르게 증가되고 있으며, 그 중에서도 태양광에너지의 분야가 가장 활발히 연구되고 있다. 특히, III-V족 화합물 반도체 태양전지는 직접 천이형 밴드갭을 가지고 있어 기존 실리콘 태양전지에 비해 광 흡수율이 높은 장점을 가지고 있다. 따라서 본 연구에서는 Molecular Beam Epitaxy (MBE)장치를 이용하여 성장온도에 따른 p-n접합 GaAs 태양전지 구조를 제작하여, 광전변환 효율과 결함구조 관련성을 조사하였다. 먼저 Si이 $1{\times}10^{18}cm^{-3}$으로 도핑된 n형 GaAs기판위에 성장온도 $480^{\circ}C$와 $590^{\circ}C$에서 Be을 $5{\times}10^{18}cm^{-3}$ 도핑한 p 형 GaAs를 200 nm 두께로 각각 성장하여, 2개의 p-n 접합 GaAs 태양전지 구조를 제작하였다. 시료의 전기적 특성과 결함상태는 Capacitance-Voltage (C-V) 와 Deep Level Transient Spectroscopy (DLTS)를 사용하여 조사하였다. DLTS 측정을 위해 p-형의 GaAs박막 위에 Au(300 nm)/Pt(30 nm)/Ti(30 nm)를 e-beam evaporator로 증착한 후, 직경 $300{\mu}m$의 메사 에칭으로 p-n접합 다이오드 구조를 제작하였다. 본 연구를 통해 GaAs p-n접합구조 성장온도에 따른 광전변환 효율과 결함상태와의 물리적인 연관성을 논의할 것이다.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.74-74
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• 2010

모바일 정보통신기기를 중심으로 전자패키지의 초소형화, 고집적화를 위해 플립칩 공법의 적용이 증가되고 있는 추세이다. 플립칩 패키징 접합소재로는 솔더, ICA(Isotropic Conductive Adhesive), ACA(Anisotropic Conductive Adhesive), NCA(Non Conductive Adhesive) 등과 같은 다양한 접합소재가 사용되고 있다. 최근에는 언더필을 사용하는 플립칩 공법보다 미세피치 대응성을 위해 NCP를 이용한 플립칩 공법에 대한 요구가 증가되고 있는데, NCP의 상용화를 위해서는 공정성과 함께 신뢰성 확보가 필요하다. 본 연구에서는 LDI(LCD drive IC) 모듈을 위한 COF(Chip-on-Film) 플립칩 패키징용 NCP 포뮬레이션을 개발하고 이를 적용한 COF 패키지의 신뢰성을 조사하였다. 테스트베드는 면적 $1.2{\times}0.9mm$, 두께 $470{\mu}m$, 접속피치 $25{\mu}m$의 Au범프가 형성된 플리칩 실리콘다이와 접속패드가 Sn으로 finish된 폴리이미드 재질의 flexible 기판을 사용하였다. NCP는 에폭시 레진과 산무수물계 경화제, 이미다졸계 촉매제를 사용하여 다양하게 포뮬레이션을 하였다. DSC(Differential Scanning Calorimeter), TGA(Thermogravimetric Analysis), DEA(Dielectric Analysis) 등의 열분석장비를 이용하여 NCP의 물성과 경화거동을 확인하였으며, 본딩 후에는 보이드를 평가하고 Peel 강도를 측정하였다. 최적의 공정으로 제작된 COF 패키지에 대한 HTS (High Temperature Stress), TC (Thermal Cycling), PCT (Pressure Cooker Test)등의 신뢰성 시험을 수행한 결과 양산 적용 가능 수준의 신뢰성을 갖는 것을 확인할 수 있었다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.6
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• pp.443-453
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• 2017

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.104.2-104.2
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• 2012

이종 재료의 접합에 대한 연구는 단일 재료에서 얻을 수 없는 물리적/기계적 특성과 이종 재료의 우수한 특성을 얻을 수 있다는 장점이 있어 국내외 적으로 연구가 활발히 진행되고 있다. 이러한 이종 접합 기술은 구조재료와 에너지 변환분야에 가장 많이 사용되고 있으며, 그 외 광촉매와 Thin film, 경량구조재료 등에도 사용되고 있다. 그 중 FGM(Functional Graded Materials)는 조성의 점진적인 변화를 통하여 접합하는 방법으로 이종 재료 접합 시 발생하는 내부 응력을 해소해줌으로써 적합한 방법이라고 할 수 있다. FGM 제작에 사용되는 방법으로 널리 알려진 것들로는 plasma spraying, 원심주조, 분말 야금법, PVD, CVD 그리고 EPD(electrophoretic deposition) 등이 있다. 이중에서 EPD는 수용액이나 유기용매와 같은 분산매체 중에 콜로이드 입자의 표면에 대전되는 전하를 이용하여, 외부에서 전장을 걸어서 입자의 움직임을 제어하는 기술이다 EPD는 코팅 속도가 상대적으로 빠르고 두꺼운 코팅 층 제작이 가능하다. 또한 바인더, 윤활제 또는 가소제를 사용하지 않고 다양한 종류와 모양의 기판 위에 균일한 코팅이 가능하다는 장점이 있다. 본 연구에서는 Ni substrate를 이용하여 그 위에 Ni과 $Al_2O_3$의 조성을 점진적으로 변화시켜 FGM을 EPD 방법으로 코팅하였다. 여기서 사용된 Ni은 높은 녹는점과 좋은 연성으로 인해 성형이 용이하여 구조재료로 적합하며, $Al_2O_3$는 고내열성과 내부식성을 가지며 경도가 높다는 장점이 있다. 본 연구에서는 EPD 방식을 이용하여 Ni/$Al_2O_3$ FGM을 코팅하였으며, 코팅 후 발생하는 substrate와의 접착력 문제를 해결하기 위해서 건조 방식과 substrate의 표면 상태를 최적화하여 다층의 Ni/$Al_2O_3$ FGM을 코팅 및 소결하였다. Zeta-potential 측정을 통해 electrophoretic mobility와 suspension의 분산 안정도를 평가 할 수 있었으며, X-ray 회절 분석(XRD)을 통하여 Ni 의 환원 여부를 확인하였다. 또한 Scanning electron microscopy(SEM) 분석을 통하여 미세구조 분석을 하였고, 최종적으로 Electron Probe Micro Analyzer (EPMA) 를 이용하여 다층 구조의 조성변화를 확인함으로 Ni/$Al_2O_3$의 FGM 코팅이 이루어졌음을 확인하였다.

• 대한공업교육학회지
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• v.33 no.1
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• pp.249-264
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• 2008

In this dissertation, shallow $p^+-n$ junctions were formed by ion implantation and dual-step annealing processes and a new simulator is designed to model boron diffusion in silicon. This simulator predicts the boron distribution after ion implantation and annealing. The dopant implantation was performed into the crystalline substrates using $BF_2$ ions. The annealing was performed with a RTA(Rapid Thermal Annealing) and a FA(Furnace Annealing) process. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of sheet resistance and the simulator reproduced experimental data successfully. Therefore, proposed diffusion simulator and FA+RTA annealing method was able to applied to shallow junction formation for thermal budget. process.

• Journal of the Korean Society for Nondestructive Testing
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• v.36 no.3
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• pp.188-194
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• 2016

We propose an acousto-optic technique for the nondestructive evaluation of adhesion properties of a Pt/Ti thin-film interface. Since there are some problems encountered when using prevailing techniques to nondestructively evaluate the interfacial properties of micro/nano-scale thin-films, we applied an interferometer that combined the acoustic and optical methods. This technique is based on the Michelson interferometer but the resultant surface of the thin film specimen makes interference instead of the mirror when the interface is excited from the acoustic transducer at the driving frequency. The thin film shows resonance-like behavior at a certain frequency range, resulting in a low-contrast fringe pattern. Therefore, we represented quantitatively the change in fringe pattern as a frequency spectrum and discovered the possibility that the interfacial adhesion properties of a thin film can be evaluated using the newly proposed technique.

• Korean Journal of Materials Research
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• v.8 no.6
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• pp.493-498
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• 1998

CdTe films were deposited by close spaced sublimation with various substrate temperatures, cell areas, and thicknesses of CdTe and ITO layers and their effects on the CdS/CdTe solar cells were investigated. The resistivity of CdTe layers employed in this study was 3$\times$ $10^{4}$$\Omega$cm For constant substrate temperature the optimum substrate ternperature for CdTe deposition was $600^{\circ}C$. To obtain larger grain size and more compact microstructure, CdTe film was initially deposited at 62$0^{\circ}C$, and then deposited at 54$0^{\circ}C$. The CdTe film was annealed at 62$0^{\circ}C$ and $600^{\circ}C$ sequentially to maintain the CdTe film quality. The photovoitaic cell efficiency improved by the "two-wave" process. For constant substrate temperature, the optimum thickness for CdTe was 5-6$\mu m$. Above 6$\mu m$ CdTe thickness, the bulk resistance of CdTe film degraded the cell performance. As the cell area increased the $V_{oc}$ remained almost constant, while $J_{sc}$ and FF strongly decreased because of the increase of lateral resistance of the ITO layer. The optimum thickness of the ITa layer in this study was 300~450nm. In this experiment we obtained the efficiency of 9.4% in the O.5cm' cells. The series resistance of the cell should be further reduced to increase the fill factor and improve the efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.16-22
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• 2002

This paper suggests the optimum processing conditions for obtaining good quality $P^{+}$-n shallow junctions formed by pre-amorphization and furnace annealing(FA) to reflow BPSG(bore phosphosilicate glass). $BF_2$ions, the p-type dopant, were implanted with the energy of 20keV and the dose of 2$\times$10$^{15}$ cm$^{-2}$ into the substrates pre-amorphized by As or Ge ions with 45keV, 3$\times$$10^{14}$ $cm^{-2}$. High temperature annealings were performed with a furnace and a rapid thermal annealer. The temperature range of RTA was 950~$1050^{\circ}C$, and the furnace annealing was employed for BPSG reflow with the temperature of $850^{\circ}C$ for 40 minutes. To characterize the formed junctions, junction depth, sheet resistance and diode leakage current were measured. Considering the preamorphization species, Ge ion exhibited better results than As ion. Samples preamorphized with Ge ion and annealed with $1000^{\circ}C$ RTA showed the most excellent characteristics. When FA was included, Ge preamorphization with $1050^{\circ}C$ RTA plus FA showed the lowest product of sheet resistance and junction depth and exhibited the lowest leakage currents.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.118-125
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• 1999

A capacitance method to extract the metallurgical channel length of LDD MOSFET's, which is defined by the length between the metallurgical junction of substrate and source/drain under the gate, is presented. The gate capacitances of the finger type and plate type LDD MOSFET gate test patterns with same total gate area are measured. The gate bias of each pattern is changed, and the capacitances are measured with source, drain, and substrate bias grounded. The differences between two test pattern's capacitance data are plotted. The metallurgical channel length is extracted from the peak data at a maximum point using a simple formula. The numerical simulation using two-dimensional device simulator is performed to verify the proposed method.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.14 no.1
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• pp.24-31
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• 2018

The mechanical design procedure is studied for the PCHE(printed circuit heat exchanger) with electrochemical etched flow channels. The effective heat transfer plates of PCHE are assembled by diffusion bonding to make a module. PCHE is widely used for industrial applications due to its compactness, cost efficiency, and serviceability at high pressure and/or temperature conditions. The limitations and technical barriers of PCHE are investigated for application to nuclear components. Rules for design and fabrication of PCHE are specified in ASME Section VIII but not in ASME Section III of nuclear components. Therefore, the calculation procedure of key dimensions of PCHE is defined based on ASME section VIII. The effective heat transfer region of PCHE is defined by several key dimensions such as the flow channel radius, edge width, wall thickness, and ridge width. The mechanical design procedure of key dimensions was incorporated into a program for easy use in the PCHE design. The effect of assumptions used in the key dimension calculation on stress values is numerically investigated. A comparative analysis is done by comparing finite element analysis results for the semi-circular flow channels with the formula based sizing calculation assuming rectangular cross sections.