• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5B
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• pp.465-475
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• 2004

Transport Control Protocol (TCP) has been implemented in software running on CPU in end systems, and the protocol processing has appeared as a new bottleneck due to advanced link technology. TCP processing is a critical issue in Storage Area Network (SAN) such as iSCSL, and the overall performance of the Storage Area Network heavily depends on speed of TCP processing. TCP Engine implemented in hardware reduces the load of CPU in end systems as well as accelerates the protocol processing, and hence high speed data processing is achieved. In this paper, we have proposed a hardware engine for TCP processing. TCP engine consists of three major block, TCP Connection block Rx TCP block and Tx TCP block TCP Connection block is responsible for managing TCP connection states. Rx TCP block is responsible for receive flow which receives packets from network and sends to CPU. Rx TCP performs header and data processing and sends header information to TCP connection block and Tx TCP block It also assembles out-of-ordered data to in-ordered before it transfers data to CPU. Tx TCP block is responsible for transmit flow which transfers data from CPU to network. Tx TCP performs retransmission for reliable data transfer and management of transmit window and sequence number. Various test-cases are used to verify the TCP functions. The TCP Engine is synthesized using 0.18 micron technology and results in 51K gates not including buffers for temporal data storage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.9
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• pp.451-458
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• 2019

Reliability in the course of weapons system development and operation is a key measure of the ability of a system to perform the required functions under specified conditions over a specified period of time, and the mission confidence for the assessment of mission fulfillment is an important indicator of victory or defeat in a battle. Mission reliability indicates the probability that a given task will succeed or fail in an event or environmental situation over a given period of time. The existing mission reliability was calculated after creating a confidence blow map with only physical connections based on the mission. However, as modern weapons systems evolve and advance, the related equipment structure becomes increasingly complex, making it impossible to express mission relevance when mission classification is required based on functional or physical connections. In this study, the mission reliability was calculated for a gun control system, which is part of a ship's combat system, by expressing the association between the physical and functional structures using the design structure matrix technique and the interface matrix technique. We expect the study results to be used as verification data for mission reliability.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.1
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• pp.52-60
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• 2002

According as many people use a computer newly, damage of computer virus and hacking is rapidly increasing by the crucial users. A computer virus is one of program in computer and has abilities of self reproduction and destruction like a virus of biology. And hacking is to rob a person's data in a intruded computer and to delete data in a Person s computer from the outside. To block hacking that is intrusion of a person's computer and the computer virus that destroys data, a study for intrusion detection of system and virus detection using a biological immune system is in progress. In this paper, we make a model of positive and negative selection for self recognition which have a similar function like T-cytotoxic cell that plays an important role in biological immune system. We embody a self-nonself distinction algorithm in computer, which is an important part when we detect an infected data by computer virus and a modified data by intrusion from the outside. And we showed the validity and effectiveness of the proposed self recognition algorithm by computer simulation about various infected data obtained from the cell change and string change in the self file.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.2
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• pp.608-616
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• 2018

If a general nonlinear system is linearized by the successive multiplication of the 1st and 2nd order systems, then there are four types of poles in this linearized system: the pole of the 1st order system and the equal poles, two distinct real poles, and complex conjugate pair of poles of the 2nd order system. Linear Quadratic (LQ) control is a method of designing a control law that minimizes the quadratic performance index. It has the advantage of ensuring the stability of the system and the pole placement of the root of the system by weighted matrix adjustment. LQ control by the weighted matrix can move the position of the pole of the system arbitrarily, but it is difficult to set the weighting matrix by the trial and error method. This problem can be solved using the characteristic equations of the Hamiltonian system, and if the control weighting matrix is a symmetric matrix of constants, it is possible to move several poles of the system to the desired closed loop poles by applying the control law repeatedly. The paper presents a method of calculating the state weighting matrix and the control law for moving the equal poles with Jordan blocks to two real poles using the characteristic equation of the Hamiltonian system. We express this characteristic equation with a state weighting matrix by means of a trigonometric function, and we derive the relation function (${\rho},\;{\theta}$) between the equal poles and the state weighting matrix under the condition that the two real poles are the roots of the characteristic equation. Then, we obtain the moving-range of the two real poles under the condition that the state weighting matrix becomes a positive semi-finite matrix. We calculate the state weighting matrix and the control law by substituting the two real roots selected in the moving-range into the relational function. As an example, we apply the proposed method to a simple example 3rd order system.

• Journal of KIISE
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• v.45 no.1
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• pp.53-60
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• 2018

This study describes a spatial web object retrieval system using Spark, an in - memory based distributed processing system. Development of social networks has created massive amounts of spatial web objects, and retrieval and analysis of data is difficult by using exist spatial web object retrieval systems. Recently, development of distributed processing systems supports the ability to analyze and retrieve large amounts of data quickly. Therefore, a method is promoted to search a large-capacity spatial web object by using the distributed processing system. Data is processed in block units, and one of these blocks is converted to RDD and processed in Spark. Regarding the discussed method, we propose a system in which each RDD consists of spatial web object index for the included data, dividing the entire spatial region into non-overlapping spatial regions, and allocating one divided region to one RDD. We propose a system that can efficiently use the distributed processing system by dividing space and increasing efficiency of searching the divided space. Additionally by comparing QP-tree with R-tree, we confirm that the proposed system is better for searching the spatial web objects; QP-tree builds index with both spatial and words information while R-tree build index only with spatial information.

• Journal of IKEEE
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• v.14 no.2
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• pp.1-8
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• 2010

In this paper, Green Mode Power IC is designed to reduce the standby power. The proposed and designed IC works for the Switch Mode Power Supply(SMPS) and has the function of PWM. To reduce the unnecessary electric power, burst mode and skip mode section are introduced and controlled by external power MOSFET to diminish the standby power. The proposed IC is designed and simulated by KEC 30V-High Voltage 0.5um CMOS Process. The structure of proposed IC is composed of voltage regulator circuit, voltage reference circuit, UVLO(Under Voltage Lock out) circuit, Ibias circuit, green circuit, PWM circuit, OSC circuit, protection circuit, control circuit, and level & driver circuit. Measuring the current consumption of each block from the simulation results, 1.2942 mA of the summing consumption current from each block is calculated and ot proved that it is within the our design target of 1.3 mA. The current consumption of the proposed IC in this paper is less than a half of conventional ICs, and power consumption is reduced to the extent of 1W in standby mode. From the above results, we know that efficiency of proposed IC is superior to the previous IC.

• Journal of The Korean Association of Information Education
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• v.24 no.1
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• pp.1-10
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• 2020

According to the Fourth Industrial Revolution, SW education is emphasized around the world to educate student with new abilities. Following to these global trends, SW education has become mandatory in Korea's 2015 revised curriculum. However, Korean elementary SW education is focused on the use of block-based programming languages. In addition, the point of view of selecting goals and organizing content of SW Education, the affective domain is ignored and focused only on the cognitive and psychomotor domains. So, this study explored method of SW education using the concept of Team-Shared Mental Model for develop of community capacity and Python, which is textual programming language gaining popularity recently. As a result of performing the post test t-test on two groups with similar Team-Shared Mental Model formation, we found that it was effective in forming a Team-Shared Mental Model of the group applying the SW teaching method suggested in the study.

• Korean Institute of Interior Design Journal
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• v.19 no.2
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• pp.197-205
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• 2010

This study examines for the processes of making a architectural significant issue of 20 cases form of Beijjng's hotel through analyzing the space composition from early the 1950's to 1992 in China. In the methods of analyzing process, We study the literatures, research reports and architectural drawings including the site survey. We hope to establish the principle in morphological characteristics and space composition of Beijing's high-rise hotels through analyzing the plan of these hotels. Finally, We find out the principles after researching. Firstly, Beijing's hotels in China faced on the being difficulties through the process of national development especially in political and economical conditions of country and peoples. Consequently, size of the Beijing's hotel developed with the fact that is complicated from that is single styles focused on the medium-sized one, modernizing popularity and the high-rise hotel buildings appeared plentifully and the form appeared with tall building putting first. Secondly, there are many immanent and interlocking styles in hotel's architectural block plans, many composition styles in big sized hotels, in opposition immanent styles in small sized ones and there are many trend of concourse style in medium sized hotels. To the layout of hotel's room inside of the linear styles are many in big and medium sized hotels.

• The Journal of the Korea Contents Association
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• v.9 no.8
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• pp.91-98
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• 2009

This paper presents a solution to error avalanche of deciphering where radio noise brings random bit errors in encrypted image data under ubiquitous environment. The image capturing module is to be made comprising data compression and encryption features to reduce data traffic volume and to protect privacy. Block cipher algorithms may experience error avalanche: multiple pixel defects due to single bit error in an encrypted message. The new fault tolerant scheme addresses error avalanche effect exploiting a three-dimensional data shuffling process, which disperses error bits on many frames resulting in sparsely isolated errors. Averaging or majority voting with neighboring pixels can tolerate prominent pixel defects without increase in data volume due to error correction. This scheme has 33% lower data traffic load with respect to the conventional Hamming code based approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.90-97
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• 2006

In this paper, we present a cost-effective architecture of high-speed soft-decision Viterbi decoder for Multi-band OFDM(MB-OFDM) systems. In the design of modem for MB-OFDM systems, a parallel processing architecture is general]y used for the reliable hardware implementation, because the systems should support a very high-speed data rate of at most 480Mbps. A Viterbi decoder also should be designed by using a parallel processing structure and support a very high-speed data rate. Therefore, we present a optimized hardware architecture for 4-way parallel processing Viterbi decoder in this paper. In order to optimize the hardware of Viterbi decoder, we compare and analyze various ACS architectures and find the optimal one among them with respect to hardware complexity and operating frequency The Viterbi decoder with a optimal hardware architecture is designed and verified by using Verilog HDL, and synthesized into gate-level circuits with TSMC 0.13um library. In the synthesis results, we find that the Viterbi decoder contains about 280K gates and works properly at the speed required in MB-OFDM systems.