• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.634-639
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• 2006

In this paper an MMIC 2-stage power amplifier is designed and fabricated for 5GHz wireless LAN applications using $0.5{\mu}m$ gate length PHEMT transistors. The PHEMT gate width is optimized in order to meet the linearity and efficiency of the MMIC power amplifier. The $0.5{\mu}m\times600{\mu}m$ PHEMT for the drive stage and $0.5{\mu}m\times3000{\mu}m$ PHEMT for the amplification stage are the optimized sizes to achieve more than 25dBc of third order IMD at the power level of 3dB back-off from the input P1dB and more than 22dBm output power under a supply voltage of 3.3V. The two-stage MMIC power amplifier is designed to be used for the both of HIPERLAN/2 and IEEE 802.11a because of its broadband characteristics. The fabricated PHEMT MMIC power amplifier exhibits a 20.1dB linear power gain, a maximum 22dBm output power, a 24% power added efficiency under 3.3V supply voltage. The input and output on-chip matching circuits are included on a chip of $1400\times1200{\mu}m^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.33-38
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• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.8
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• pp.1817-1823
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• 2009

A design of cascaded distributed amplifier with a broadband amplification is described in this paper. A medium power device with 23dBm, max output power under the optimal narrow-band power matching condition is adopted for the design and fabrication of the cascaded distributed amplifier. In general, conventional distributed amplifiers with the parallel connected input ports have a low gain, and previous cascaded distributed amplifiers show a relatively low output power of 10dBm at most, which is the upper limit of small signal amplification. However, the cascaded distributed amplifier in this paper shows the gain of $18.15{\pm}0.75dB$ and output power of 20dBm over $300MHz{\sim}2GHz$ from the measurement, so it can be well adopted as a wideband driver amplifier.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.43-46
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• 2012

In this paper, high efficiency power amplifier is implemented with high gain amplifier. Two-stage amplifier using adaptive bias control circuit improve efficiency at low input power. Fixed bias circuit and adaptive bias circuit both have about 76 % efficiency at maximum power level. However amplifier using an adaptive bias control circuit has 70 % at 6 dBm input power level when the amplifier using fixed bias circuit has 50%. The proposed power amplifier using the adaptive bias control circuit can have high efficiency at lower power level.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.1
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• pp.84-92
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• 2000

A GaAs MESFET MMIC transmitter for 2.4 GHz wireless local loop handset is designed and fabricated. The transmitter consists of a double balanced active mixer and a two stage driver amplifier with voltage negative feedback. In particular, a pair of CS-CG(common source-common gate) structure compensates the reduction in dynamic range caused by unbalanced complementary IF input signals. And to suppress the leakage local power at RF port, the mixer is designed by using phase characteristic between the ports of MESFET. At the bias condition of 2.7 V and 55.2 mA, the fabricated MMIC transmitter with chip dimensions of $0.75\times1.75 mm^2$ obtains a measured conversion gain of 38.6 dB, output $P_{idB}$ of 11.6 dBm, and IMD3 at -5 dBm RF output power of -31.3 dBc. This transmitter is well suited for WLL handset.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.85-96
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• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.2
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• pp.72-75
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• 2012

In this paper, high-efficiency DC-AC converter is implemented for the wireless power transmission. The DC-AC converter is implemented by combining the oscillator and power amplifier. Because the conversion efficiency of wireless power transmitter is strongly affected by the efficiency of power amplifier, the high-efficiency power amplifier is implemented by using the Class-E amplifier structure. Also, because the output power of oscillator connected to the input stage of power amplifier is low, high-gain two-stages power amplifier using the drive amplifier is implemented to realize the high-output power DC-AC converter. The dual band harmonic suppression filter is implemented to suppress 2nd, 3rd harmonics of 13.56 MHz. The output power and conversion efficiency of DC-AC converter are 40 dBm and 80.2 % at the operation frequency of 13.56 MHz.

• Journal of Sensor Science and Technology
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• v.5 no.6
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• pp.25-34
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• 1996

In this paper, we have designed signal conditioning circuitry for piezoresistive pressure sensor. Signal conditioning circuitry consists of voltage reference circuit for sensor driving voltage and instrument amplifier for sensor signal amplification. Signal conditioning circuitry is simulated using HSPICE in a single poly double metal $1.5\;{\mu}m$ BiCMOS technology. Simulation results of band-gap reference circuit showed that temperature coefficient of $21\;ppm/^{\circ}C$ at the temperature range of $0\;{\sim}\;70^{\circ}C$ and PSRR of 80 dB. Simulation results of BiCMOS amplifier showed that dc voltage gain, offset voltage, CMRR, CMR and PSRR are outperformed to CMOS and Bipolar, but power dissipation and noise voltage were more improved in CMOS than BiCMOS and Bipolar. Designed signal conditioning circuitry showed high input impedance, low offset and good CMRR, therefore, it is possible to apply sensor and instrument signal conditioning circuitry.

• Journal of the Korean Society for Nondestructive Testing
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• v.25 no.1
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• pp.15-19
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• 2005

Conventional eddy current testing has been used for the detection of the defect-like fatigue crack in the conductive materials, such as aluminum, which uses a sinusoidal signal with very narrow frequency bandwidth, Whereas, the pulsed eddy current method uses a pulse signal with a broad bandwidth. This can allow multi-frequency eddy current testing, and the penetration depth is greater than that of the conventional eddy current testing. In this work, a pulsed eddy current instrument was developed for evaluating the metal loss. The developed instrument was composed of the pulse generator generating the maximum square pulse voltage of 40V, an amplifier controlled up to 52dB, an A/D converter of 16 bit and the sampling frequency of 20 MHz, and an industrial personal computer operated by the Windows program. A pulsed eddy current probe was designed as a pancake type in which the sensing roil was located inside the driving roil. The output signals of the sensing roil increased rapidly wich the step pulse driving voltage かn off, and the latter part of the sensing coil output voltage decreased exponentially with time. The decrement value of the output signals increased as the thickness of the aluminum test piece increased.