• Title/Summary/Keyword: 공통회로

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Post-Linearization Technique of CMOS Cascode Low Noise Amplifier Using Dual Common Gate FETs (두 개의 공통 게이트 FET를 이용한 캐스코드형 CMOS 저잡음 증폭기의 후치 선형화 기법)

  • Huang, Guo-Chi;Kim, Tae-Sung;Kim, Seong-Kyun;Kim, Byung-Sung
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.7 s.361
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    • pp.41-46
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    • 2007
  • A novel post-linearization technique is proposed for CMOS cascode low noise amplifier (LNA). The technique uses dual common gate FETs one of which delivers the linear currents to a load and the other one sinks the $3^{rd}$ order intermodulation currents of output currents from the common source FET. Selective current branching can be implemented in $0.18{\mu}m$ CMOS process by using a thick oxide FET as an IM3 sinker with a normal FET as a linear current buffer. A differential LNA adopting this technique is designed at 2.14GHz. The measurement results show 11dBm IIP3, 15.5dB power gain and 2.85dB noise figure consuming 12.4mA from 1.8V power supply. Compared with the LNA with turning off the IM3 sinker, the proposed technique improves the IIP3 by 7.5 dB.

A 2-Dimensional Approach for Analyzing Variability of Domain Core Assets (도메인 핵심자산의 가변성 분석을 위한 2차원적 접근방법)

  • Moon Mi-Kyeong;Chae Heung-Seok;Yeom Keun-Hyuk
    • Journal of KIISE:Software and Applications
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    • v.33 no.6
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    • pp.550-563
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    • 2006
  • Software product line engineering is a method that prepares for the future reuse and supports to seamless reuse in application development process. Commonality and variability play central roles in all product line development processes. Reusable assets will become core assets by explicitly representing C&V. Indeed, the variabilities that art identified at each phase of core assets development have different levels of abstraction. In the past, these variabilities have been handled in an implicit manner and without distinguishing the characteristics of each core assets. In addition, previous approaches have depended on the experience and intuition of a domain expert to recognize commonality and variability. In this paper, we suggest a 2-dimensional analyzing method that analyzes the variabilities of core assets in software product line. In horizontal analysis process, the variation types are analyzed in requirements, architecture, and component that are produced at each phase of development process. In vertical analysis process, variations are analyzed in different abstract levels, in which the region of commonality is identified and the variation points are refined. By this method, the traceability of variations between core assets will be possible and core assets can be reused seamlessly.

High-linearity voltage-controlled current source circuits with wide range current output (넓은 범위의 전류 출력을 갖는 고선형 전압-제어 전류원 회로)

  • 차형우
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.7
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    • pp.89-96
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    • 2004
  • High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gain control are proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0㎃ to 300㎃ over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than 1.4% over the current range from 0A to 300㎃.

Correlation Analysis of Runoff and Water Quality Factor of the Seolma-Cheon Experimental Catchment (2006년 설마천 시험유역의 유량과 수질인자의 상관관계 분석)

  • Kim, Dong-Phil;Kim, Sung-Hoon
    • Proceedings of the Korea Water Resources Association Conference
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    • 2007.05a
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    • pp.865-869
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    • 2007
  • 본 논문의 목적은 설마천 시험유역을 대상으로 2006년의 신뢰성 있는 수문 수질자료를 바탕으로 유역의 유출거동에 따른 수질인자와의 상관관계를 분석하는데 있다. 시험유역에서는 10분 단위의 연속적인 우량 및 수위관측과 연간 30회 이상의 유량측정성과를 통하여 수위-유량관계곡선식을 개발하여 유량을 산정하고 있으며, 수질분석을 위한 시료는 유량측정시 전적비교, 사방교 지점에서 샘플을 채취하여 실험실에서 분석하였다. 실험실에서 분석한 항목은 pH, DO, BOD, COD, T-N, T-P, SS로 총 7개 항목으로 수질측정은 우기가 시작된 시기인 7월에 집중적으로 측정 분석하였으며, 7월 이후에도 각 지점당 6회의 추가 측정으로 각각 22회의 시료를 채취하여 분석하였다. 분석된 수질자료를 이용하여 2개 측정지점에 대하여 각 항목간의 상관관계를 분석하였으며, 홍수기 및 갈수기로 기간을 구분하여 각 항목간의 상관관계를 분석하였다. 2개 지점의 상관관계 분석결과 BOD는 T-P와 SS, COD는 T-N과 SS가 공통적으로 상관관계가 높은 것으로 나타나 전적비교와 사방교의 유기물 농도가 SS와 비례하는 것으로 나타났다. 또한 전적비교와 사방교간 홍수기의 상관관계를 살펴보면 COD는 T-N, SS와 그리고 SS는 COD와 공히 상관관계가 높으며 갈수기도 COD와 SS의 상관관계가 같이 높은 것으로 분석되었다.

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Design of Intra Prediction Circuit for HEVC and H.264 Multi-decoder Supporting UHD Images (UHD 영상을 지원하는 HEVC 및 H.264 멀티 디코더 용 인트라 예측 회로 설계)

  • Yu, Sanghyun;Cho, Kyeongsoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.12
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    • pp.50-56
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    • 2016
  • This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.

Analysis of Relationship between GPs and SPs in CMMI Maturity Level 2 and Verifying the Applicable Efficiency (CMMI 성숙도 2단계 GP와 SP간 상호 연관성 분석 및 적용 효율성 검증)

  • Lee, Min-Jae;Rhew, Sung-Yul;Kim, Sung-Tae
    • Journal of KIISE:Software and Applications
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    • v.37 no.6
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    • pp.480-485
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    • 2010
  • In the characteristics of CMMI architectures and components, there are many relations among CMMI practices. The organizations can be more efficiently improving their processes if they understand relationship among CMMI practices. However, there are no researches regarding this topic yet. In this paper we analyzed the relationship between Generic Practices and Specific Practices of each process areas in CMMI Maturity Level 2 by using Chi-square test of independence. As a result, we demonstrated that 10 Generic Practices in each process area are related 17 out of 48 Specific Practices (35% relationship). Using this result to improve the organization's processes, we achieved a significant improvement of 36.5% in CMMI appraisal result.

A CMOS LC VCO with Differential Second Harmonic Output (차동 이차 고조파 출력을 갖는 CMOS LC 전압조정발진기)

  • Kim, Hyun;Shin, Hyun-Chol
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.6 s.360
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    • pp.60-68
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    • 2007
  • A technique is presented to extract differential second harmonic output from common source nodes of a cross-coupled P-& N-FET oscillator. Provided the impedances at the common source nodes are optimized and the fundamental swing at the VCO core stays in a proper mode, it is found that the amplitude and phase errors can be kept within $0{\sim}1.6dB$ and $+2.2^{\circ}{\sim}-5.6^{\circ}$, respectively, over all process/temperature/voltage corners. Moreover, an impedance-tuning circuit is proposed to compensate any unexpectedly high errors on the differential signal output. A Prototype 5-GHz VCO with a 2.5-Hz LC resonator is implemented in $0.18-{\mu}m$ CMOS. The error signal between the differential outputs has been measured to be as low as -70 dBm with the aid of the tuning circuit. It implies the push-push outputs are satisfactorily differential with the amplitude and phase errors well less than 0.34 dB and $1^{\circ}$, respectively.

Low Power 4-Gb/s Receiver for GND-referenced Differential Signaling (접지기반 차동신호 전송을 위한 저전력 4-Gb/s 수신단 설계)

  • Lee, Mira;Kim, Seok;Jeong, Youngkyun;Bae, Jun-Han;Kwon, Kee-Won;Chun, Jung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.9
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    • pp.244-250
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    • 2012
  • This paper describes a 4-Gb/s receiver circuit for a low-swing ground-referenced differential signaling system. The receiver employs a common-gate level-shifter and a continuous linear equalizer which compensates inter-symbol-interference (ISI) and improves voltage and timing margins. A bias circuit maintains the bias current of the level-shifter when the common level of the input signal changes. The receiver is implemented with a low-power 65-nm CMOS technology. When 4-Gb/s 400mVp-p signals are transmitted to the receiver through the channel with the attenuation of -19.7dB, the timing margin based on bit error rate (BER) of $10^{-11}$ is 0.48UI and the power consumption is as low as 0.30mW/Gb/s.

Comparative antigen analysis of yrichomonus vaginulis by enzyme-linked immunoelectrotransfer blot technique (효소면역 전기영동 이적법을 이용한 질트리코모나스 항원의 비교 분석)

  • 민득영;임미혜
    • Parasites, Hosts and Diseases
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    • v.30 no.4
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    • pp.323-328
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    • 1992
  • Analysis of siR isolates of Trichemenes veginalis was carried out with sodium dodecyl sulfate- polyacrylamide gel electrophoresis (SDS-PAGE) and enzyme-linked immunoelectrotransfer blot (EITB). Trichloroacetic acid-treated antigens of the 6 isolates revealed 25 protein profiles ranging 12~170 kDa of molecular weight in SDS-PAGE. In EITB, the specific immunogenic bands were visualized at 51 kDa and 96 kDa when HY-1 antigen was probed with difFerent mice sera immunized with 6 isolates of T. vaginalis. The banding patterns with different sera showed isolate-to-isolate variability. In EITB, homologous antigen (HY-1) did not show any enhanced response in reacting to homologous antiserum(HY-1) when 6 isolates of T. vaginalis were probed with a single serum (HY-1). It is assumed that the different banding patterns of six isolates show isolate-to-isolate variability and immunogenic common bands in 41, 47, 74 and 9:k kDa on EITB may connote the important significance on immune response in T. vaginalis infection.

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Protein Interaction Network Visualization System Combined with Gene Ontology (유전자 온톨로지와 연계한 단백질 상호작용 네트워크 시각화 시스템)

  • Choi, Yun-Kyu;Kim, Seok;Yi, Gwan-Su;Park, Jin-Ah
    • Journal of KIISE:Computer Systems and Theory
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    • v.36 no.2
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    • pp.60-67
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    • 2009
  • Analyzing protein-protein interactions(PPI) is an important task in bioinformatics as it can help in new drugs' discovery process. However, due to vast amount of PPI data and their complexity, efficient visualization of the data is still remained as a challenging problem. We have developed efficient and effective visualization system that integrates Gene Ontology(GO) and PPI network to provide better insights to scientists. To provide efficient data visualization, we have employed dynamic interactive graph drawing methods and context-based browsing strategy. In addition, quick and flexible cross-reference system between GO and PPI; LCA(Least Common Ancestor) finding for GO; and etc are supported as special features. In terms of interface, our visualization system provides two separate graphical windows side-by-side for GO graphs and PPI network, and also provides cross-reference functions between them.