• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2480-2486
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• 2012

The design of low voltage LC-VCO(LC Voltage Controlled Oscillator) has been presented to optimize the phase noise and power consumption for the block of frequency synthesis to satisfy WCDMA system specification in this paper. The parameters for minimum phase noise has been obtained in the region of design, using the lines of the tuning range and the excess gain in the plane of the inductance and the transconductance of MOS transistor to compensate the loss of LC-tank. As a result of simulation, the phase noise characteristics is -113dBc/Hz for offset of 1MHz. The optimum designed LC-VCO has been fabricated using the process of 0.25um CMOS. As a result of measurement for fabricated chip, the phase noise characteristics is -116dBc/Hz for offset of 1MHz. The power consumption is 15mW, and Kvco is 370MHz/V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.43-49
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• 2000

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications ate presented. The circuit approach is based on the characteristic of the LV(Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by 0.6${\mu}{\textrm}{m}$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to $\pm$0.5V with a linearity error of less than 1%. The measured -3㏈ bandwidth is 290MHz and the power dissipation is 373㎼. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.1-7
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• 2008

This paper proposes 3.3V input and 1.8V output voltage mode step-down DC-DC buck converter for wireless mobile system which is designed in a standard 0.35$\mu$m CMOS process. The proposed capacitor multiplier method can minimize error amplifier compensation block size by 30%. It allows the compensation block of DC-DC converter be easily integrated on a chip. Also, we improve efficiency to 3% using low power buffer. Measurement result shows that the circuit has less than 1.17% output ripple voltage and maximum 83.9% power efficiency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.39-39
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• 2008

이동통신 시스템의 소형화, 다기능화 추세에 따라 이동통신 부품들의 모듈화, 고집적화 추세로 급진전되고 있어, 고집적 세라믹 기판 모듈 제작을 위한 핵심공정 기술인 그린시트의 층간 정밀도 및 소성후 수축율 제어의 중요성이 증대되고 있다. 본 연구에서는 일축가압 이용한 PAS(Pressure Assisted Sintering) 법과 Al2O3를 희생층으로 이용한 Constrained Sintering법을 혼합하여 저온 동시소성 세라믹 기판의 x-y 축 수축율을 zero로 제어하고자하였다. $Al_2O_3$/LTCC/$Al_2O_3$인 샌드위치 구조로 세라믹 시트를 적층하여 Load 값과, LTCC 두께에 따른 x-y축, z축 소성 수축율 및 Edge Curvature의 Radius와 warpage 현상을 관찰하고, 이때 미세구조 및 밀도를 측정하였다. 그 결과 symmetic한 구조일 때 소성온도 $900^{\circ}C$에서 $Al_2O_3$ 두께가 $30{\mu}m$ 이상일 때 LTCC의 글라스가 $Al_2O_3$에 Infiltration 되는 두께는 $30{\mu}m$를 나타내었다. 또한 $Al_2O_3$ 두께 $500{\mu}m$, LTCC 두께 $2,000{\mu}m$, Load값이 800g/$cm^2$ 일 때 x-y 축 수축율<1%, z축 수축율 40%, 소결밀도는 2.99g/$cm^3$로 우수한 무수축 기판 특성을 나타내었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.77-83
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• 2009

In this paper, a selective feedback low-noise amplifier (LNA) has been realized in a $0.18{\mu}m$ CMOS technology to cover a number of wireless multi-standards. By exploiting notch filter, the SF-LNA demonstrates the measured results of the power gain (S21) of 11.5~13dB and the broadband input/output impedance matching of less than -10dB within the frequency bands of 820~960MHz and 1.5~2.5GHz, respectively. The chip dissipates 15mW from a single 1.8V supply, and occupies the area of $1.17\times1.0mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.1-7
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• 2012

A 9b MS/s CMOS cyclic folding A/D converter (ADC) for intelligent battery sensor and battery management systems is proposed. The proposed ADC structure is based on a cyclic architecture to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolating structure. The prototype ADC implemented with a 0.35um 2P4M n-well CMOS process shows a measured INL and DNL of maximum 1.5LSB and 1.0LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 48dB and 60dB, respectively, and the power consumption is about 110mW at 2MS/s and 3.3V. The occupied active die area is $10mm^2$.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.72-78
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• 1998

An optical modulator Ti:LiNbO$_3$optical waveguide and CPW electrode structure were fabricated. The optical modulator was packaged using components such as ferrules, dirmy LN block and glass, vibration and shock absorbption pad, and alumina feeder through processings of pigtailing. Au wire bonding, epoxing, SMA connecting, sealing. The electrical and optical characteristics were measured after packaging. The electrical properties of S$_{21}$ and S$_{11}$ were obtained as 9.8 GHz at -3 dB and -8.9dB at 14.4GHz, respectively. Optical waveguide prepared met requirements for a single mode at a 1550nm wavelength range. Insertion loss was 4.3dB at room temperature after packaging, and was varied 4.3~6.4dB at various temperatures, 5~45$^{\circ}C$. E-O bandwidth measurement showed 3dB optical response at 7.8GHz, which means that it is applicable for 10Gbps optical communicationon

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.7
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• pp.731-736
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• 2012

A new method for producing boron-containing nanoparticles is described. Boron trichloride ($BCl_3$) and methane ($CH_4$) are dissociated through injection into a thermal plasma followed by a nucleation process producing boron or boron carbide nanoparticles. X-ray photoelectron spectroscopy was used to detect B-C bonds related to the carbide state and to probe the ratio of boron to carbon in the B-C bond structure. In addition, nanoparticles were characterized with scanning transmission electron microscopy and electron energy loss spectroscopy. It was found that nanoparticles were in the range 30-70 nm and a boron to carbon ratio in the B-C bond structure of up to 2 can be reached when $BCl_3$ of 20 sccm and $CH_4$ of 25 sccm were used.