• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3178-3180
• /
• 1999

초음파 진단기의 신호처리에 필요한 8-b 해상도와 40MS/s 이상의 변환속도를 갖는 ADC를 Folding and Interpolating 형태로 설계했다. 전력소모와 입력단의 오프셋에 의한 영향을 줄이기 위해 프리엠프의 출력을 Interpolation하여 그 개수를 절반으로 줄임으로써 전력소모를 줄였고, 기존의 전압모드 Interpolation 회로에서의 단순한 source follower를 정궤환을 이용한 버퍼의 형태로 바꾸어 이득을 개선시킴으로써 전압의 이용율을 높일 수 있었다. ADC에서 가장 중요한 비교기를 설계함에 있어서는 다이나믹 전력 소모만 있는 구조에 킥-백 노이즈를 줄이기 위한 설계를 했다 $0.6{\mu}m$ CMOS 공정을 이용해 설계되었고, Layout 결과 칩의 면적은 $1.3mm{\times}1.3mm$. 모의 실험결과 40MS/s에서 70mw의 전력을 소모하였다.

• Journal of IKEEE
• /
• v.13 no.4
• /
• pp.9-14
• /
• 2009

This paper describes measurement of an on-ship power supply noise in mixed-signal integrated circuits. To measure the on-chip power supply noise, we can check the effects of analog circuits and compensate it. This circuit consists of two independent measurement channels, each consisting of a sample and hold circuit and a frequency to digital converter which has a buffer and voltage controlled oscillator(VCO). The time-based voltage information and frequency-based power spectrum density(PSD) can be achieved by a simple analog to digital conversion scheme. The buffer works like a unit-gain buffer with a wide bandwidth and VCO has a high gain to improve resolution. This circuit was fabricated in a 0.18um CMOS technology and has 2.06mV/count. The noise measurement circuit consumes 15mW and occupies $0.768mm^2$.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.1
• /
• pp.33-38
• /
• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.21-21
• /
• 2006

21세기 정보통신 및 관련 소재의 연구방향은 새로운 기능성 확보, 극한적 제어성, 복합 및 융합이라는 경향으로 발전해 가고 있다. 반도체 기술 분야에서 현재의 공정적 한계를 극복하고 새로운 기능성을 부여하기 위해 나노 합성과 배열을 기본으로 하여 bottom-up 방식의 나노소자 구현이 큰 주목을 받고 있다. 나노선의 경우 나노 스케일의 dimension, 양자 제한 효과, 우수한 결정성, self-assembly, internal stress 등 기존 벌크형 소재에서 발견할 수 없는 새로운 기능성이 나타나고 있어 바이오, 에너지, 구조, 전자, 센서 등의 분야에서의 활용이 가능하다. 현재 국내외적으로 반도체 나노선으로 널리 연구되고 있는 재료는 ZnO, $SnO_2$, SiC 등이 중심이 되고 있다. 이중 ZnO 나 노선의 합성을 위해서는 thermal CVD, MOCVD, PLD, wet-chemical 등 다양한 방법이 사용되고 있다. 특히 MOCVD 방법에 의해 수직 정렬된 ZnO 나노막대를 성장할 수 있다. 이러한 나노막대는 MO 원료 및 산소 공급량을 적절히 제어함으로서 수직 배향 및 나노선의 구경 제어가 가능하며, 나노 막대의 크기 제어와 관련해서는 반응 관내의 DEZn 와 $O_2$의 양을 변화시켜 구조체의 크기를 수 십 ~ 수 백 나노미터의 크기로 제어할 수 있다. 본 연구는 이러한 ZnO 나노선의 성장과정에서 $210^{\circ}C$ 이하의 저온에서 성장한 ZnO 버퍼층을 이용해 나노구조의 형상을 제어하고자 하였다. 특히 ZnO 저온 버퍼층의 두께에 따라 나노막대의 직경변화, 수직배향성, 형상변화의 제어가 가능하였다. 나노막대의 특성 평가는 TEM, SEM, PL, XRD 등을 이용하여 구조적, 결정학적, 광학적 특성을 분석하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.9
• /
• pp.1-7
• /
• 2008

This paper proposes 3.3V input and 1.8V output voltage mode step-down DC-DC buck converter for wireless mobile system which is designed in a standard 0.35$\mu$m CMOS process. The proposed capacitor multiplier method can minimize error amplifier compensation block size by 30%. It allows the compensation block of DC-DC converter be easily integrated on a chip. Also, we improve efficiency to 3% using low power buffer. Measurement result shows that the circuit has less than 1.17% output ripple voltage and maximum 83.9% power efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.6
• /
• pp.1194-1201
• /
• 2003

Measurements of network traffic have shown that self-similarity is a ubiquitous phenomenon spanning across diverse network environments. We have advance the framework of multiple time scale congestion control and show its effectiveness at enhancing performance for fast TCP prototype control. In this paper, we extend the fast TCP prototype control framework to window-based congestion control, in particular, TCP. This is performed by interfacing TCP with a large time scale control module which adjusts the aggressiveness of bandwidth consumption behavior exhibited by TCP as a function of "large time scale" network state. i.e., conformation that exceeds the horizon of the feedback loop as determined by RTT. Performance evaluation of fast TCP prototype is facilitated by a simulation bench-mark environment which is based on physical modeling of self-similar traffic. We explicate out methodology for discerning and evaluating the impact of changes in transport protocols in the protocol stack under self-similar traffic conditions. We discuss issues arising in comparative performance evaluation under heavy-tailed workload. workload.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.3
• /
• pp.21-29
• /
• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.89-95
• /
• 2008

In this paper, we designed a low power face detection hardware and analysed its power consumption. The face detection hardware was fabricated using Samsung 0.18um CMOS technology and it can detect multiple face locations from a 2-D image. The hardware is composed of 6 functional modules and 11 internal memories. We introduced two operating modes(SLEEP and ACTIVE) to save power and a clock gating technique was used at two different levels: modules and registers. In additional, we divided an internal memory into several pieces to reduce the energy consumed when accessing memories, and fully utilized low power design option provided in Synopsis Design Compiler. As a result, we could obtain 68% power reduction in ACTIVE mode compared to the original design in which none of the above low power techniques were used.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.8
• /
• pp.717-724
• /
• 2016

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.6
• /
• pp.1166-1174
• /
• 2004

In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.