• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.87-92
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• 2006

An $AB^2$ modular operation is an efficient basic operation for the public key cryptosystems and various systolic architectures for $AB^2$ modular operation have been proposed. However, these architectures have a shortcoming for cryptographic applications due to their high area complexity. Accordingly, this paper presents an partitioned $AB^2$ systolic modular multiplier over GF($2^m$). A dependency graph from the MSB $AB^2$ modular multiplication algorithm is partitioned into 1/3 to get an partitioned $AB^2$ systolic multiplier. The multiplier reduces the area complexity about 2/3 compared with the previous multiplier. The multiplier could be used as a basic building block to implement the modular exponentiation for the public key cryptosystems based on smartcard which has a restricted hardware requirements.

• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.131-133
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• 2004

이 논문에서는 MPEG audio 알고리즘의 필터뱅크를 덧셈을 사용하여 저전력으로 구현할 수 있는 구조를 제안하였다. 제안된 구조는 CSD(Canonic Signed Digit) 형의 계수를 사용하며, 입력신호 샘플을 최대로 공유함으로서 사용되는 덧셈기의 수를 최소화하였다. 제안된 구조는 알고리즘에서 사용된 공통입력 공유, 선형위상 대칭 필터계수를 이용한 공유, 공통입력을 이용한 블록 공유, CSD 형의 계수와 공통패턴 공유를 통하여 사용되는 덧셈의 수를 최소화할 수 있음을 보였다. Verilog-HDL 코딩을 통하여 시뮬레이션을 수행한 결과, 제안된 구조는 기존의 곱셈기 구조의 구현면적과 비교하여 $59.6\%$를 감소시킬 수 있음을 보였다. 또한 제안된 구조의 전력소모도 곱셈기 구조와 비교하여 $59.6\%$를 감소시킬 수 있음을 보였다. 따라서 곱셈기가 내장된 DSP 프로세서를 사용하지 않고도, Arithmetic Unit나 마이크로프로세서를 사용하여 효과적으로 MPEG audio 필터뱅크를 구현할 수 있음을 보였다.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.112-117
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• 2004

In this paper, we propose a suitable multiplication architecture for cellular automata in a finite field $GF(2^m)$. Proposed least significant bit first multiplier is based on irreducible all one Polynomial, and has a latency of (m+1) and a critical path of $ 1-D_{AND}＋1-D{XOR}$.Specially it is efficient for implementing VLSI architecture and has potential for use as a basic architecture for division, exponentiation and inverses since it is a parallel structure with regularity and modularity. Moreover our architecture can be used as a basic architecture for well-known public-key information service in $GF(2^m)$ such as Diffie-Hellman key exchange protocol, Digital Signature Algorithm and ElGamal cryptosystem.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.87-94
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• 2002

In this paper an asynchronous away multiplier with a parallel array structure is introduced. This parallel array structure is used to make the computation time faster with a lower Power consumption. Asymmetric parallel away structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional booth encoding array structures and that the multiplier with the proposed away structure shows a reduction of 40% in the computational time with a relatively lower power consumption.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.521-523
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• 2003

본 논문에서는 프로그램 가능한 셀룰라 오토마타(Programmable Cellular Automata, PCA)를 이용한 곱셈기를 제안한다. 본 논문에서 제안한 구조는 연산 후 늘어나는 원소의 수를 제한하기 위하여 이용되는 기약다항식(irreducible polynomial)으로서 All One Polynomial(AOP)을 사용하며, 주기적 경계 셀룰라 오토마타(Periodic Boundary Cellular Automata, PBCA)의 구조적인 특성을 사용함으로써 정규성을 높이고 하드웨어 복잡도와 시간 복잡도를 줄일 수 있는 장점을 가지고 있다. 제안된 곱셈기는 시간적. 공간적인 면에서 아주 간단히 구성되어 지수연산을 위한 하드웨어 설계나 오류 수정 코드(error correcting code)의 연산에 효율적으로 이용될 수 있을 것이다.

• School Mathematics
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• v.13 no.2
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• pp.267-286
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• 2011

In this paper I investigated the historical developments of the algorithms for multiplication of natural numbers. Through this analysis I tried to describe more concretely what is to understand the common algorithm for multiplication of natural numbers. I found that decomposing dividends and divisors into small numbers and multiplying these numbers is the main strategy for carrying out multiplication of large numbers, and two decomposing and multiplying processes are very important in the algorithms for multiplication. Finally I proposed some implications based on these analysis.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.64-71
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• 2014

Multiplier performs a complex arithmetic operation in various signal processing algorithms such as multimedia and communication system. The multiplier also suffers from its relatively large signal propagation delay, high power dissipation, and large area requirement. This paper presents memristor-CMOS based reconfigurable multiplier reducing area occupation of the multiplier circuitry and increasing compatibility using optimized bit-width for various applications. The performance of the memristor-CMOS based reconfigurable multiplier are estimated with memristor SPICE model and 180 nm CMOS process under 1.8 V supply voltage. The circuit shows performance improvement of 61% for area, 38% for delay and 28% for power consumption respectively compared with the conventional reconfigurable multipliers. It also has an advantage for area reduction of 22% against a twin-precision multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.80-86
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• 2003

Elliptic curve cryptosystem(ECC) offers the highest security per bit among the known publick key system. The benefit of smaller key size makes ECC particularly attractive for embedded applications since its implementation requires less memory and processing power. In this paper, we propose a new multiplier structure with configurable output sizes and operation cycles. The number of output bits can be freely chosen in the new architecture with the performance-area trade-off depending on the application. Using the architecture, a 193-bit normal basis multiplier and inversion unit are designed in GF(2$^{m}$ ). It is implemented using HDL and 0.35${\mu}{\textrm}{m}$ CMOS technology and the operation is verified by simulation.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.1-9
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• 2004

The important arithmetic operations over finite fields include exponentiation, division, and inversion. An exponentiation operation can be implemented using a series of squaring and multiplication operations using a binary method, while division and inversion can be performed by the iterative application of an AB$^2$ operation. Hence, it is important to develop a fast algorithm and efficient hardware for this operations. In this paper presents new bit-serial architectures for the simultaneous computation of multiplication and squaring operations, and the computation of an $AB^2$ operation over $GF(2^m)$ generated by an irreducible AOP of degree m. The proposed architectures offer a significant improvement in reducing the hardware complexity compared with previous architectures, and can also be used as a kernel circuit for exponentiation, division, and inversion architectures. Furthermore, since the Proposed architectures include regularity and modularity, they can be easily designed on VLSI hardware and used in IC cards.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1297-1308
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• 2006

Multiplications in finite fields are one of the most important arithmetic operations for implementations of elliptic curve cryptographic systems. In this paper, we propose a new multiplication algorithm and VLSI architecture over $GF(2^m)$ using Gaussian normal basis. The proposed algorithm is designed by using a symmetric property of normal elements multiplication and transforming coefficients of normal elements. The proposed multiplication algorithm is applicable to all the five recommended fields $GF(2^m)$ for elliptic curve cryptosystems by NIST and IEEE 1363, where $m\in${163, 233, 283, 409, 571}. A new VLSI architecture based on the proposed multiplication algorithm is faster or requires less hardware resources compared with previously proposed normal basis multipliers over $GF(2^m)$. In addition, we gives an easy method finding a basic multiplication matrix of normal elements.