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Asynchronous Multiplier with Parallel Array Structure  

Park, Chan-Ho (Electronics and Telecommunications Research Institute)
Choe, Byeong-Su (Dept. of Information Communication Engineering, Gwangju Institute of Science and Technology)
Lee, Dong-Ik (Dept. of Information Communication Engineering, Gwangju Institute of Science and Technology)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.5, 2002 , pp. 87-94 More about this Journal
Abstract
In this paper an asynchronous away multiplier with a parallel array structure is introduced. This parallel array structure is used to make the computation time faster with a lower Power consumption. Asymmetric parallel away structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional booth encoding array structures and that the multiplier with the proposed away structure shows a reduction of 40% in the computational time with a relatively lower power consumption.
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