Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Asynchronous Multiplier with Parallel Array Structure

병렬배열구조를 사용한 비동기 곱셈기

  • Park, Chan-Ho (Electronics and Telecommunications Research Institute) ;
  • Choe, Byeong-Su (Dept. of Information Communication Engineering, Gwangju Institute of Science and Technology) ;
  • Lee, Dong-Ik (Dept. of Information Communication Engineering, Gwangju Institute of Science and Technology)
  • 박찬호 (한국전자통신연구원) ;
  • 최병수 (광주과학기술원 정보통신공학과) ;
  • 이동익 (광주과학기술원 정보통신공학과)
  • Published : 2002.05.01
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Abstract

In this paper an asynchronous away multiplier with a parallel array structure is introduced. This parallel array structure is used to make the computation time faster with a lower Power consumption. Asymmetric parallel away structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional booth encoding array structures and that the multiplier with the proposed away structure shows a reduction of 40% in the computational time with a relatively lower power consumption.

본 논문에서는 기존의 배열구조의 문제점인 전력낭비와 느린 연산속도를 보완하기 위하여 병렬배열구조를 채택하고 비동기 시스템에 적합하도록 평균 연산속도를 최소화한 곱셈기를 제안한다. 실험 결과 제안된 비대칭 병렬배열구조는 기존의 배열구조와 비교하였을 때, 평균 55% 정도의 연산시간 단축이 가능하며, 이 구조를 이용한 Booth 인코딩 비동기 곱셈기는 기존의 Booth 인코딩 배열 곱셈기에 비해 40% 정도의 시간 단축 효과가 있음을 확인하였다.

Keywords

References

  1. C.S. Wallace, A suggestion for fast multiplication technique, IEEE Transaction on Electronic Computer, Vol. EC-13, pp. 14-17, Feb. 1964 https://doi.org/10.1109/PGEC.1964.263829
  2. I.E.Sutherland, Micropipelines, Communications of ACM, Vol. 32, No. 6, pp. 720-738, Jan. 1989 https://doi.org/10.1145/63526.63532
  3. The standard Performance Evaluation Corporation. SPEC CPU95 Benchmarks. SPEC Newsletter, September 1995
  4. D. Burger, T.M Austin, and S. Bennett, Evaluating future microprocessors : The sim-plescalar tool set, Tech. Rep. CS-TR-96-1308, University of Wisconsin-Madison, July, 1996
  5. Introduction to Shade, Sun Microsystem Laboratories, Inc. TR 415-960-1300, Revision A of l/Apr/92
  6. 김영수, 차영호, 조경연, 최혁환, Leading 0/1 검출 기능을 부가한 곱셈기, IEEK Summer Conference 2000 컴퓨터그룹, pp. 85-88, June 2000
  7. S. E. McQuillan, J. V. McCanny, A, VLSI architecture for multiplication, division and square root, International Conference on Acoustics, Speech, and Signal Processing, pp. 1205-1208, 1991 https://doi.org/10.1109/ICASSP.1991.150600
  8. A. D. Booth. A signed binary multiplication technique, Quarterly J. Mechanics, Appl. Math, Vol. 4, Part 2, pp. 236-240, 1951 https://doi.org/10.1093/qjmam/4.2.236
  9. K. Muhammad, D. Somasekhar and K. Roy, Switching characteristics of generalized array multiplier architecture and their application to low power design, International Conference on Computer Design (ICCD), 1999 https://doi.org/10.1109/ICCD.1999.808430
  10. David Kearney and Neil W. Bergmann, Bundled Data Asynchronous Multiplier with Data Dependent Computation times, Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 186-197, April 1997
  11. Israel Koren, Computer Arithmetic Algorithm, Prentice Hall International, 1993
  12. Pascal C.H. Meier, Rob A Rutenbar, L.Richard Carley, Inverse Polarity Techniques for Hgh-Speed/Low-Power Multipliers, International Symposium on Low Power Electronics and Design, pp. 264-266, August 1999