• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.79-90
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• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.3
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• pp.419-426
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• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.6-11
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• 2007

This paper proposes CMOS optical receivers to reduce effective area and pulse width distortion (PWD) in high definition digital audio interfaces. To mitigate effective area and PWD, proposed receivers include a frans-impedance amplifier (TIA) with dual output and a level shifter with threshold convergence, respectively. Proposed circuits are fabricated using $0.25{\mu}m$ CMOS process and measured result demonstrated the effective area of $270\times120{\mu}m^2$ and PWD of ${\pm}3%$ for the receiver with a dual output TIA, and the effective area of $410\times140{\mu}m^2$ and PWD of ${\pm}2%$ for the receiver with a threshold convergence level shifter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.5
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• pp.509-516
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• 2004

High-performance Si integrated passive process was developed using thick oxidation process and Cu-BCB process. This passive process leads to low-cost and high-quality RF module with a small form factor. The fabricated spiral inductor with 225 um inner diameter and 2.5 turns showed the inductance of 2.7 nH and the quality factor more than 30 in the frequency region of 1 ㎓ and above. Also WLCSP-type integrated passive devices were fabricated using the high-performance spiral inductors. The fabricated low pass filter had a parallel-resonance circuit inside the spiral inductor to suppress 2nd harmonics and showed about 0.5 ㏈ insertion loss at 2.45 ㎓. And also the high/low-pass balun had the insertion loss less than 0.5 ㏈ and the phase difference of 182 degrees at 2.45 ㎓.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.122-123
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• 2011

본 논문에서는 분산전원시스템에서 계통의 전력품질 향상 및 분산전원과 계통의 전력흐름(Power flow)을 제어 할 수 있는 대역통과필터(BPF: Band Pass Filter)하나만을 사용하는 분산전원용 저가격 순시전력제어기를 제안한다. 제안된 시스템은 1개의 BPF만을 사용하여 무효전력보상 및 전력흐름을 제어함으로써 복잡한 행렬 연산 없이 순시제어가 가능한 장점으로 고성능 연산장치 또는 곱셈기와 같은 부가회로 없이 회로구성을 할 수 있어 저가격으로 회로구현이 가능하다. 제안된 시스템의 유용성을 확인하기 위해 시뮬레이션을 수행하였다.

• KIISE Transactions on Computing Practices
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• v.22 no.4
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• pp.163-169
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• 2016

Lustre is a scalable, distributed file system, which is popular in the field of high-performance computing. Recently, the advent of SSD has enabled high-performance storage hardware, but software development requires further improvement. In this paper, we analyzed performance of the Lustre system using SSD via extensive experimentation. We compared performance of Lustre on SSDs and HDDs in terms of file read/write throughputs and metadata access latencies. Our experimental results showed that 1) SSDs improve metadata access performance due to fast random read/write access of SSD characteristics, and 2) SSD are benefited to a greater extent under multiple threads and large numbers of small sized files.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.8
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• pp.763-767
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• 2008

In this paper, to make a high performance and low power CORDIC architecture for 3D operations in mobile devices, we suggest two off-line vectoring algorithms named Angle Based Search (ABS) and Scaling Considered Search (SCS). The ABS algorithm represents a 3D vector with two angles and those angles are used as a condition for searching CORDIC rotation sequences. The SCS algorithm determines the best CORDIC rotation sequence in advance to eliminate extra scaling computation. Using the proposed algorithms, we can observe 50% of latency is reduced. Furthermore, we perform a simple analysis and discuss possible reduction of power consumption by applying voltage scaling method together with the proposed algorithm.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.6
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• pp.10-18
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• 2007

In consideration of increment and importance for data, an efficient and large storage backup system requires. Existing backup system solutions show some limitations in speed and technical. In order to solve these deficiencies, backup and recovery system of high efficiency and large storage capacity was designed and implemented by using high speed, compression technique and backup accelerator etc. Backup and recovery system applies to multi-threading, multi-processing and multi-streaming technology. And already established systems based on tape, but proposed backup operating model designed on disk. Therefore, the implemented of system leads to these backup media problems as well as solutions to aforementioned issues with existing backup system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.191-196
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• 2016

Recently, power dissipation is a very significant issue not only in embedded systems and mobile devices but also in high-end modern processors. Especially, by the prevalent use of smart phones and tablet PCs, low power consumption of microprocessors is requisite. In this paper, a fast power measurement tool for a high performance microprocessor based on the trace-driven simulator has been developed. The power model of the microprocessor consists of complex combinational circuits, array structures, and CAM structures. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation of each program.