• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.83-91
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• 2000

This paper presents a new technique to reduce a large interconnect circuit with tens of thousands of elements into the one that is small enough to be analyzed by circuit simulators such as SPICE. This technique takes a fundamentally different approach form the conventional methods based on the interconnect circuit structure analysis and several rules based on the Elmore time constant. The time moments are computed form the circuit consisting of the interconnect circuit and the CMOS gate driver model computed by the AWE technique. Then, the equivalent RC circuit is synthesized from those moments. The characteristics of the driving CMOS gate can be reflected with the high degree of accuracy and the size of the compressed circuit is determined by the number of output nodes regardless of the size of the original interconnect circuits. This technique has been implemented in C language, applied to several interconnect circuits driven by a 0.5${\mu}m$ CMOS gate and the equivalent RC circuits with more than 99% reduction ratio and accuracy with 1 ~ 10% error in therms of propagation delays were obtained.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.48-52
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• 1998

We fabricated the newly proposed nano structure memory with SOI edge channel and a nano dot. The width of the edge channel of this device, which uses the side wall as a channel and has a nano dot on this channel region, was determined by the thickness of the recessed top-silicon layer of SOI wafer. The size of side-wall nano dot was determined by the RIE etch and E-Beam lithography. The I$_{d}$-V$_{d}$, I$_{d}$-V$_{g}$ characteristics of the devices without nano dots and memory characteristics of the devices with nano dots were obtained, where the voltage scan was done between -20 V and 14 V and the threshold voltage shift was about 1 V.t 1 V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.737-739
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• 2010

In this paper, the subthreshold characteristics have been alanyzed using MicroTec4.0 for double gate MOSFET(DGMOSFET). The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. The oxide thickness and channel thickness in DG MOSFET determines threshold voltage and extensively influences on Ss(Subthreshold swing). We have investigated the threshold voltage and Ss(Subthreshold swing) characteristics according to variation of channel thickness from 1nm to 3nm in this study.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1717-1723
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• 2007

In this study , quasi-MFISFET (Metal-Ferroelectric-Insulator-Semiconductor FET) devices are fabricated using PLZT(10/30/70), PLT(10), PZT(30/70) thin film and their drain current properties are investigated. It is found that the drain current of quasi-MFISFET is directly influenced by the polarization strength of ferroelectric thin fan. Also, when the gate voltages are ${\pm}5\;and\;{\pm}10V$, the memory windows are 0.5 and 1.3V, respectively. It means that the memory window is changed with the variation of coercive voltage generated by the voltage applied on ferroelectric thin film. The electric field and the leakage current with time delay of PLZT(10/30/70) thin lam are measured to investigate the retention property of MFISFET device. Some material parameters such as current density constant, $J_{ETO}$, electric field dependent factor K and time dependent factor m are obtained. The variation of charge density with time is quantitatively analyzed by using the material parameters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.584-597
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• 2011

In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1380-1386
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• 2009

In this paper, we propose a CQS(Calendar Queue Scheduler) architecture which was designed for processing multimedia and timing traffic in home network. With various characteristics of the increased traffic flowed in home such as VoIP, VOD, IPTV, and Best-efforts traffic, the needs of managing QoS(Quality of Service) are being discussed. Making a group regarding application or service is effective to guarantee successful QoS under the restricted circumstances. The proposed design is aimed for home gateway corresponding to the end points of receiver on end-to-end QoS and eligible for supporting multimedia traffic within restricted network sources and optimizing queue sizes. Then, we simulated the area for each module and each memory. The area for each module is referenced by NAND($2{\times}1$) Gate(11.09) when synthesizing with Magnachip 0.18 CMOS libraries through the Synopsys Design Compiler. We verified the portion of memory is 85.38% of the entire CQS. And each memory size is extracted through CACTI 5.3(a unit in mm2). According to the increase of the memory’sentry, the increment of memory area gradually increases, and defining the day size for 1 year definitely affects the total CQS area. In this paper, we discussed design methodology and operation for each module when designing CQS by hardware.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.93-101
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• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.47-52
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• 2008

As the packing density of IC devices gets ever higher, the thickness of the gate $SiO_2$ layer of the MOS devices is now required to be reduced down to 1 nm. For such a thin $SiO_2$ layer, the MOS device cannot operate properly because of tunneling current and threshold voltage shift. Hence there has been much effort to develop new dielectric materials which have higher dielectric constants than $SiO_2$ and is free from such undesirable effects. In this work, the physical and electrical characteristics of ALD $ZrO_2$ film have been studied. After deposition of a thin ALD $ZrO_2$ film, it went through thermal treatment in the presence of argon gas at $800^{\circ}C$ for 1 hr. The characteristics of morphology, crystallization kinetics, and interfacial layer of $Pt/ZrO_2/Si$ samples have been investigated by using the analyzing instruments like XRD, TEM and C-V plots. It has been found that the characteristics of the $Pt/ZrO_2/Si$ device was enhanced by the thermal treatment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.6
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• pp.1460-1464
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• 2010

In the paper, the breakdown voltage of Trench D-MOSFET have been analyzed by using MircoTec. The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. A Trench MOSFET is the most preferred power device for high voltage power applications. The oxide thickness and doping concentration in Trench MOSFET determines breakdown voltage and extensively influences on high voltage. We have investigated the breakdown voltage characteristics according to variation of doping concentration from $10^{15}cm^{-3}$ to $10^{17}cm^{-3}$ in this study. We have also investigated the breakdown voltage characteristics according to variation of oxide thickness and junction depth.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.