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Implementation and verification of H.264 / AVC Intra Predictor for mobile environment  

Yun, Cheol-Hwan (Dept. of Electronics and Communications Engineering, Kwangwoon University)
Jeong, Yong-Jin (Dept. of Electronics and Communications Engineering, Kwangwoon University)
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Abstract
Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.
Keywords
H.264 / AVC; Intra Prediction; small area; single arithmetic unit;
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