• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.1
• /
• pp.1-6
• /
• 2004

Dry etch characteristics of polysilicon with HBr/O$_2$ inductively coupled plasma (ICP) have been investigated. We determined etch late, uniformity, etch profiles, and selectivity with analyzing the cross-sectional scanning electron microscopy images obtained from top, center, bottom, right, and left positions. The etch rate of polysilicon was about 2500 $\AA$/min, which meets with the mass production for devices. The wafer level etch uniformity was within $\pm$5 ％. Etch profile showed 90$^{\circ}$ slopes without notches. The selectivity over photoresist was between 2:1∼4.5:1, depending on $O_2$ flow rate. The HBr-ICP etching showed higher PR selectivity, and sharper profile than the conventional Cl$_2$-RIE.

• Journal of Sensor Science and Technology
• /
• v.19 no.2
• /
• pp.137-141
• /
• 2010

In this paper, we fabricated silicon piezoresistive pressure sensor with dry etching technology which used Deep-RIE and etching delay technology which used SOI(silicon-on-insulator) wafer. We improved pressure sensor offset and its temperature dependence by removing oxidation layer of SOI wafer which was used for dry etching delay layer. Sensitivity of the fabricated pressure sensor was about 0.56 mV/V${\cdot}$kPa at 10 kPa full-scale, and nonlinearity of the fabricated pressure sensor was less than 2 %F.S. The zero off-set change rate was less than 0.6 %F.S.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.53 no.2
• /
• pp.62-66
• /
• 2004

This paper investigated the characteristics of a newly developed high density hollow cathode plasma (HCP) system and its application for the etching of silicon wafers. We used SF$_{6}$ and $O_2$ gases in the HCP dry etch process. Silicon etch rate of $0.5\mu\textrm{m}$/min was achieved with $SF_6$$O_2$plasma conditions having a total gas pressure of 50mTorr, and RF power of 100 W. This paper presents surface etching characteristics on a crystalline silicon wafer and large area cast type multicrystlline silicon wafer. The results of this experiment can be used for various display systems such as thin film growth and etching for TFT-LCDs, emitter tip formations for FEDs, and bright plasma discharge for PDP applications.s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11a
• /
• pp.247-251
• /
• 2004

반도체 소자의 제조에 있어 실리콘 표면에 성장한 자연산화막을 제거하기 위해 일반적으로 습식 세정 기술이 이용되어 왔다. 하지만 소자의 최소 선폭(design rule)이 nano급으로 고집적화 됨에 따라 contact hole 바닥의 자연산화막을 깨끗이 제거하는데 있어서 그 한계를 나타나고 있다. 이에 대한 효과적인 대안 공정으로 가스 건식 세정 기술이 연구되고 있다. 본 논문에서는 한 번에 50매 이상의 웨이퍼를 처리함으로써 생산성 측면에서 월등한 배치식 설비에서 원거리 플라즈마(remote plasma) 장치에서 2.450Hz의 마이크로웨이브(${\mu}$-wave)에 의해 형성시킨 수소라디칼과 $NF_3$ 가스를 이용하여 실리콘에 결함을 주지 않고 자연산화막을 선택적으로 제거하는 공정에 대해 고찰하였다. AFM을 이용한 표면분석, TEM을 이용한 물성분석, 그리고 ToF-SIMS 및 XPS를 이용한 화학 분석을 습식 및 건식 세정을 비교 평가한 결과, 건식 세정 공정이 실리콘 표면에 결함을 주지 않고 자연산화막을 제거 할 수 있음을 확인하였다. 산화막$(SiO_2)$, 질화막$(Si_3N_4)$, 그리고 다결정 실리콘(Poly-Si) 등의 각 막질별 식각 특성을 고찰하였으며, $NH_3$의 캐리어 가스인 $N_2$의 주입량을 조절함으로써 수소라디칼 형성 효율의 개선이 가능하였으며, 이로부터 게이트와 소스/드레인 사이를 절연하기 위해 이용되는 질화막의 식각 선택비를 2배 정도 개선할 수 있었다. nano급 소자에 실장하여 평가한 결과에서 불산(HF)에 의한 습식 세정 방식에 비하여 약 $20{\sim}50%$ 정도의 contact 저항 감소 효과가 있음이 확인되었다.두 소자 모두 $40mA/cm^2$ 에서 이상적인 화이트 발란스와 같은(0.33,0.33)의 색좌표를 보였다.epsilon}_0=1345$의 빼어난 압전 및 유전특성과 $330^{\circ}C$의 높은 $T_c$를 보였고 그 조성의 vibration velocity는 약4.5 m/s로 나타났다.한 관심이 높아지고 있다. 그러나 고 자장 영상에서의 rf field 에 의한 SAR 증가는 중요한 제한 요소로 부각되고 있다. 나선주사영상은 SAR 문제가 근원적으로 발생하지 않고, EPI에 비하여 하드웨어 요구 조건이 낮아 고 자장에서의 고속영상방법으로 적합하다. 본 논문에서는 고차 shimming 을 통하여 불균일도를 개선하고, single shot 과 interleaving 을 적용한 multi-shot 나선주사영상 기법으로 $100{\times}100$에서 $256{\times}256$의 고해상도 영상을 얻어 고 자장에서 초고속영상기법으로 다양한 적용 가능성을 보였다. 연구에서 연구된 $[^{18}F]F_2$가스는 친핵성 치환반응으로 방사성동위원소를 도입하기 어려운 다양한 방사성의 약품개발에 유용하게 이용될 수 있을 것이다.었으나 움직임 보정 후 영상을 이용하여 비교한 경우, 결합능 변화가 선조체 영역에서 국한되어 나타나며 그 유의성이 움직임 보정 전에 비하여 낮음을 알 수 있었다. 결론: 뇌활성화 과제 수행시에 동반되는 피험자의 머리 움직임에 의하여 도파민 유리가 과대평가되었으며 이는 이 연구에서 제안한 영상정합을 이용한 움직임 보정기법에 의해서 개선되었다. 답이 없는 문제, 문제 만들기, 일반화가 가능한 문제 등으로 보고, 수학적 창의성 중 특히 확산적 사고에 초점을 맞추어 개방형 문제가 확

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.10
• /
• pp.106-112
• /
• 1990

The progress of oxidation of a porous silicon layer(PSL) was studied by examining the temperature dependence of the oxidation and the infrared absorption spectra. Thick OPSL(oxidized porous silicon layer). which has the same properties as thermal $SiO_{2}$ of bulk silicon, is formed in a short time by two steps wet oxidation of PSL at $700^{\circ}C$, 1 hr and $1100^{\circ}C$, 1 hr. Etching rate, breakdown strength of the OPSL are strongly dependent on the oxidation temperature, oxidation atmosphere. And its breakdown field was ${1\MV/cm^-2}$ MV/cm The oxide film stress was determined through curvature measurement using a dial gauge. During oxidation at temperature above $1000^{\circ}C$ in dry $O_{2}$, stress on the order of ${10^9}\dyne/{cm^2}{-10^10}\dyne/{cm^2}$ are generated in the OPSL.

• Applied Chemistry for Engineering
• /
• v.8 no.3
• /
• pp.395-402
• /
• 1997

The $SiO_2$ films were prepared by ECR(electron cyclotron resonance) plasma diffusion method, Deal-Grove model and Wolters-Zegers-van Duynhoven model were used to estimate the oxidation rate which was correlated with surface morphology for different orientation of Si(100) and Si(111). It was seen the $SiO_2$ thickness increased linearly with initial oxidation time. But oxidation rate slightly decrease with oxidation time. It was also shown that the oxidation process was controlled by the diffusion of the reactive species through the oxide layer rather than by the reaction rate at the oxide interface. The similar time dependency has been observed for thermal and plasma oxidation of silicon. From D-G model and W-Z model, the oxidation rate of Si(111) was 1.13 times greater than Si(100) because Si(111) had higher diffusion and reaction rate, these models more closely fits the experimental data. The $SiO_2$ surface roughness was found to be uniform at experimental conditions without etching although oxidation rate was increased, and to be nonuniform due to etching at experimental condition with higher microwave power and closer substrate distance.

• Journal of the Korean Vacuum Society
• /
• v.6 no.2
• /
• pp.103-108
• /
• 1997

Silicon field emitter arrays (FEAs) have been fabricated by a novel method employing a two-step tip etch and a spin-on-glass (SOG) etch-back process using double layered thermal/tetraethylortho-silicate (TEOS) oxides as a gate dielectric. A partial etching was performed by coating a low viscous photo resist and $O_2$ plasma ashing on order to form the double layered gate dielectric. A small gate aperture with low gate leakage current was obtained by the novel process. The hight and the end radius of the fabricated emitter was about 1.1 $\mu\textrm{m}$ and less than 100$\AA$, respectively. The anode emission current from a 256 tips array was turned-on at a gate voltage of 40 V. Also, the gate current was less than 0.1% of the anode current.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.16 no.12 s.117
• /
• pp.1272-1278
• /
• 2006

This paper presents a novel MEMS condenser microphone with rigid backplate to enhance acoustic characteristics. The MEMS condenser microphone consists of membrane and backplate chips which are bonded together by gold-tin(Au/Sn) eutectic solder bonding. The membrane chip has $2.5mm{\times}2.5mm$, 0.5${\mu}m$ thick low stress silicon nitride membrane, $2mm{\times}2mm$ Au/Ni/Cr membrane electrode, and 3${\mu}m$ thick Au/Sn layer. The backplate chip has $2mm{\times}2mm$, 150${\mu}m$ thick single crystal silicon rigid backplate, $1.8mm{\times}1.8mm$ backplate electrode, and air gap, which is fabricated by bulk micromachining and silicon deep reactive ion etching. Slots and $50{\sim}60{\mu}m$ radius circular acoustic holes to reduce air damping are also formed in the backplate chip. The fabricated microphone sensitivity is 39.8 ${\mu}V/Pa$(-88 dB re. 1 V/Pa) at 1 kHz and 28 V polarization voltage. The microphone shows flat frequency response within 1 dB between 20 Hz and 5 kHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.243-243
• /
• 2010

This paper two different etching, HF : HNO3 :DI and RIE were used for etching in multi-crystalline Silicon(Mc-Si) solar cell fabrication. The wafers etched in RIE texture showed low reflectance compared to the wafers etched in Acid soultion after SiNx deposition. In light current-voltage results, the cells etched in RIE texture exhibited higher short circuit current and open circuit voltage than those of the cells etched in acid solution. We have obtained 15.1% conversion efficiency in large area($156cm^2$) Multi-Si solar cells etched in RIE texture.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.1
• /
• pp.31-43
• /
• 1993

Thermal behavior and $O_{2}$ plasma effects on residue and penetrated impurities formed by reactive ion etching (RIE) in CHF$_{3}$/C$_{2}$F$_{6}$ have been investigated using X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS) techniques. Decomposition of polymer residue film begins between 200-300.deg. C, and above 400.deg. C carbon compound as graphite mainly forms by in-situ resistive heating. It reveals that thermal decomposition of residue can be completed by rapid thermal anneal above 800.deg. C under nitrogen atmosphere and out-diffusion of penetrated impurities is observed. The residue layer has been removed with $O_{2}$ plasma exposure of etched silicon and its chemical bonding states have been changed into F-O, C-O etc.. And $O_{2}$ plasma exposure results in the decrease of penetrated impurities.