• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.53-60
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• 2009

A low-power/small-area 128-point FFT processor is designed, which is based on logarithmic number system (LNS) and some design techniques to minimize both hardware complexity and arithmetic error. The complex-number multiplications and additions/subtractions for FFT computation are implemented with LNS adders and look-up table (LUT) rather than using conventional two's complement multipliers and adders. Our design reduces the gate counts by 21% and the memory size by 16% when compared to the conventional two's complement implementation. Also, the estimated power consumption is reduced by about 18%. The LNS-based FFT processor synthesized with 0.35 ${\mu}m$ CMOS standard cell library has 39,910 gates and 2,880 bits memory. It can compute a 128-point FIT in 2.13 ${\mu}s$ with 60 MHz@2.5V, and has the average SQNR of 40.7 dB.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.27-35
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• 1999

In a typical spread spectrum system, parallel correlator occupies a large fraction of power consumption because of the large number of accumulators in the system. In this paper, a novel accumulator is proposed that can reduce the power consumption in the parallel correlator. The proposed accumulator counts the numbers of 1 of the incoming input data. The counted values are weighted and added together to obtain the final correlation value only at the end of the accumulation. The proposed accumulator has been designed and simulated by CADENCE Verilog-XL and synthesized by SYNOPSYS Design Compiler with $0.6{\mu}m$ standard cell library. Power consumption results have been obtained from EPIC PowerMill simulations. Simulation results are very encouraging. First, the power dissipation is reduced by 22% and the maximum operating frequency is increased by 323%. In addition, the parallel correlator using the proposed accumulators consumed less power than the conventional active parallel correlators by 22%, and less power than the conventional passive correlator by 43%.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.48-57
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• 2003

In this paper, An 8${\times}$l ID-IDCT processor with adder-based distributed arithmetic(DA) and bit-serial method Is presented. To reduce hardware cost and to improve operating speed, the proposed 8${\times}$1 ID-IDCT used the bit-serial method and DA method. The transform of coefficient equation results in reduction in hardware cost and has a regularity in implementation. The sign extension computation method reduces operation clock. As a result of logic synthesis, The gate count of designed 8${\times}$1 1D-IDCT is 17,504. The sign extension processing block has gate count of 3,620. That is 20% of total 8${\times}$1 ID-IDCT architecture. But the sign extension processing block improves more than twice in throughput. The designed IDCT processes 50Mpixels per second and at a clock frequency of 100MHz.

• The Journal of the Acoustical Society of Korea
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• v.15 no.1
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• pp.46-53
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• 1996

Adaptive LMS algorithm has been used in many application areas due to its low complexity. In this paper input signal is transformed into the subbands with arbitrary bandwidth. In each subbands the dynamic range can be reduced, so that the independent filtering in each subbands has faster convergence rate than the full band system. The DCT transform domain LMS adaptive filtering has the whitening effect of input signal at each bands. This leads the convergence rate to very high speed owing to the decrease of eigen value spread Finally, the filtered signals in each subbands are synthesized for the output signal to have full frequency components. In this procedure wavelet filter bank guarantees the perfect reconstruction of signal without any interspectra interference. In simulation for the case of speech signal added additive white gaussian noise, the suggested algorithm shows better performance than that of conventional NLMS algorithm at high SNR.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• The Journal of the Korea Contents Association
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• v.8 no.7
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• pp.182-194
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• 2008

This study seeks to intensively shed light on the municipal police system which is certain to be introduced to the nation, and verify the effect of the new appointment system presented herein from the viewpoint of police and experts in related areas, thus contributing to having the municipal police system in place stably. In particular, this study sets as the most core factors the recruiting, selection, education and training, and placement in the process of a new appointment, centered on Municipal Police Introduction (Plan) submitted to the National Assembly. First, in the area of recruiting and adoption, presented the head or manager of the municipal police implements open administrative job recruiting system, expanded recruiting of women and manpower in special recruitment to administer citizen-friendly police administration, and the exclusive employment rights of the head of the municipality. Second, in the area of the education and training of the municipal police as to the securing of independent education and training agencies, establishment of curricula fit for characteristics of the municipal police, and utilization of education facilities and professors of regional universities. Finally, in the case of the placement of the municipal police as to side effects caused by the placement of region-hailing personnel, implementation of interview system prior to a new placement, and priority placement of policewomen to the civil service section.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.213-220
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• 2011

In this paper, the channel preprocessor with an area-efficient architecture is proposed for the MIMO symbol detector which can support four transmit and receive antennas. The proposed channel preprocessor can shrink the channel dimension to reduce the hardware complexity of the MIMO symbol detector. Also, the proposed channel preprocessor is implemented with very low complexity by using QR decomposition (QRD) and log-number system (LNS). By applying QRD and LNS to the nulling matrix calculation block, the numbers of matrix-multiplications and matrix-divisions are decreased and thus the complexity of the proposed channel preprocessor is significantly reduced. The proposed channel preprocessor was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. With the proposed channel preprocessor, the number of logic gates for channel preprocessor is reduced by 20.2% compared with the conventional architecture.