• Proceedings of the KIEE Conference
• /
• 1995.11a
• /
• pp.338-341
• /
• 1995

The surface properties after plasma etching of Al(Si, Cu) solutions using the chemistries of chlorinated and fluorinated gases with varying the etching time have been investigated using X-ray Photoelectron Spectroscopy. Impurities of C, Cl, F and O etc are observed on the etched Al(Si, Cu) films. After 95% etching, aluminum and silicon show metallic states and oxized (partially chlorinated) states, copper shows Cu metallic states and Cu-Clx(x$CuCl_x$ (x$CuCl_x$ (1

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.7-8
• /
• 2007

We investigated the characteristics of UTB-SOI pMOSFETs with SOI thickness ($T_{SOI}$) ranging from 10 nm to 1 nm and evaluated the dependence of electrical characteristics on the silicon surface orientation. As a result, it is found that the subthreshold characteristics of (100)-surface UTB-SOI pMOSFETs were superior to (110)-surface. However, the hole mobility of (110)-surface were larger than that of (100)-surface. The enhancement of effective hole mobility at the effective field of 0.1 MV/ccm was observed from 3-nm to 5-nm SOI thickness range.

• Proceedings of the Korean Society of Laser Processing Conference
• /
• 2003.05a
• /
• pp.107-110
• /
• 2003

• Proceedings of the Korean Magnestics Society Conference
• /
• 2010.06a
• /
• pp.165-166
• /
• 2010

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1065-1068
• /
• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.8
• /
• pp.23-28
• /
• 2010

In this paper, comparative analysis of digital and analog performances of strained-silicon PMOSFETs with different carrier direction were performed. ID.SAT vs. ID.OFF and output resistance, Rout performances of devices with <100> carrier direction were better than those of <110> direction due to the greater carrier mobility of <100> channel direction. However, on the contrary, NBTI reliability and device matching characteristics of device with <100> carrier direction were worse than those with <110> carrier direction. Therefore, simultaneous consideration of analog and reliability characteristics as well as DC device performance is highly necessary when developing mobility enhancement technology using the different carrier direction for nano-scale CMOSFETs.

• Proceeding of EDISON Challenge
• /
• 2017.03a
• /
• pp.412-416
• /
• 2017

CMOS device에서 off leakage current로 인한 power dissipation 문제는 미래 소자에 주어진 주요한 과제이다. Nanowire FET은 이러한 문제를 해결할 주요 미래소자로 각광받고있다. 하지만 nanowire FET을 공정할 때 채널 에칭을 완벽한 원형 구조로 가지는 것이 어렵기 때문에 타원형으로 시뮬레이션을 진행해 볼 필요성이 있다. 본 논문에서는 nanowire의 aspect ratio, crystal orientation의 변화에 따른 nanowire FET의 전압-전류 특성 및 transport 특성을 관찰하는 연구를 진행하였다. 시뮬레이션 결과, [100] 방향은 완벽한 원형구조에서 최적인 반면에 [110] 방향은 타원형으로 모델링함에 있어서 장점이 있는 것으로 나타났다.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.383-383
• /
• 2010

Gas-phase hydrogen atoms create a variety of chemical and physical phenomena on Si surfaces: adsorption, abstraction of pre-adsorbed H, Si etching, Si amorphization, and penetration into the bulk lattice. Thermal desorption/evolution analyses exhibited three distinct peaks, including one from the crystalline bulk. It was previously found that thermal-energy gaseous H(g) atoms penetrate into the Si(100) crystalline bulk within a narrow substrate temperature window(centered at ~460K) and remain trapped in the bulk lattice before evolving out at a temperature as high as ~900K. Developing and sustaining atomic-scale surface roughness, by H-induced silicon etching, is a prerequisite for H absorption and determines the $T_s$ windows. Issues on the H(g) absorption to be further clarified are: (1) the role of the detailed atomic surface structure, together with other experimental conditions, (2) the particular physical lattice sites occupied by, and (3) the chemical nature of, absorbed H(g) atoms. This work has investigated and compared the thermal H(g) atom absorptivity of Si(100), Si(111) and Si(110) samples in detail by using the temperature programmed desorption mass spectrometry (TPD-MS). Due to the differences in the atomic structures of, and in the facility of creating atom-scale etch pits on, Si(100), (100) and (110) surfaces, the H-absorption efficiency was found to be larger in the order of Si(100) > Si(111) > Si(110) with a relative ratio of 1 : 0.22 : 0.045. This intriguing result was interpreted in terms of the atomic-scale surface roughening and kinetic competition among H(g) adsorption, H(a)-by-H(g) abstraction, $SiH_3(a)$-by-H(g) etching, and H(g) penetraion into the crystalline silicon bulk.

• Proceedings of the Korean Society for Technology of Plasticity Conference
• /
• 2006.05a
• /
• pp.77-80
• /
• 2006

Structural phase transformations of silicon during nanoindentation were investigated in detail at the atomic level. The molecular dynamics simulations of nanoindentation on the (100), (110) and (111) surface of single crystalline silicon were simulated, and this supported the theoretical prediction of the anisotropic behavior of structural phase transformations. Simulations showed that microscopic aspects of phase transformation varied according to the crystallographic orientation of the contact surface and were directly linked to the slip system.

• Journal of the Korean Ceramic Society
• /
• v.36 no.8
• /
• pp.863-870
• /
• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.