• 센서학회지
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• 제22권2호
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• pp.130-135
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• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.956-959
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• 2001

In die and mould industry, major material such as cemented carbide is broadly used for increasing the life time and decreasing the cost. It is also required the development for the skills of wire-cut electrical discharge machining(WEDM), but the WEDMed surface was found to be worst due to the attached components of wire. Precision machining method like lapping is necessary for obtaining high quality surface. The lapping compound such as Al2O3 and SiC and cast iron lap can be used for lapping process. The components of Cu and Zn were found WEDMed surface of the specimen. As the result, the low quality of precision was obtained and the heat damage layer of the specimen was occurred. The value of surface hardness was deteriorated, and therefore finish process was required.

• 한국광학회:학술대회논문집
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• 한국광학회 2000년도 하계학술발표회
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• pp.188-189
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• 2000

1차원 자성 포토닉 결정은 결함 층으로 삽입된 자성 층에 빛이 국재화되어 거대한 자기광학 효과를 나타낸다. 그 구조를 적절하게 설계하면 원하는 파장에서 거대한 자기광학 효과와 큰 투과율을 얻을 수 있다는 점에서 주목을 받고 있다. [1] 본 연구에서는 (A/B)$_{k}$ M/(A/B)$_{k}$ 의 구조를 갖는(여기서 A는 SiO$_2$, M은 Bi:YIG) 1차원 자성 포토닉 결정에 대해 B유전체 층의 굴절율을 변화시켰을 때의 투과율(T), 페러데이 회전각 ($ heta$$_{F}$ ), 성능지수(Q)를 수치 해석한 결과를 보고한다. (중략)

• 한국재료학회지
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• 제20권11호
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• pp.600-605
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• 2010

In order to meet the requirements of faster speed and higher packing density for devices in the field of semiconductor manufacturing, the development of Cu/Low k device material is explored for use in multi-layer interconnection. SiOC(-H) thin films containing alkylgroup are considered the most promising among all the other low k candidate materials for Cu interconnection, which materials are intended to replace conventional Al wiring. Their promising character is due to their thermal and mechanical properties, which are superior to those of organic materials such as porous $SiO_2$, SiOF, polyimides, and poly (arylene ether). SiOC(-H) thin films containing alkylgroup are generally prepared by PECVD method using trimethoxysilane as precursor. Nano voids in the film originating from the sterichindrance of alkylgroup lower the dielectric constant of the film. In this study, methyltriphenylsilane containing bulky substitute was prepared and characterized by using NMR, single-crystal X-ray, GC-MS, GPC, FT-IR and TGA analyses. Solid-state NMR is utilized to investigate the insoluble samples and the chemical shift of $^{29}Si$. X-ray single crystal results confirm that methyltriphenylsilane is composed of one Si molecule, three phenyl rings and one methyl molecule. When methyltriphenylsilane decomposes, it produces radicals such as phenyl, diphenyl, phenylsilane, diphenylsilane, triphenylsilane, etc. From the analytical data, methyltriphenylsilane was found to be very efficient as a CVD or PECVD precursor.

• Transactions on Electrical and Electronic Materials
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• 제9권4호
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• pp.169-172
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• 2008

We attempted to fabricate carbon nanotube field effect transistor (CNT-FET) using single walled carbon nanotube(SWNT) on the heavily doped Si substrate used as a bottom gate, source and drain electrode were fabricated bye-beam lithography on the 500 nm thick $SiO_2$ gate dielectric layer. We investigated electrical and physical properties of this CNT-FET using Scanning Probe Microscope(SPM) and conventional method based on tungsten probe tip technique. The gate length of CNT-FET was 600 nm and the diameter of identified SWNT was about 4 nm. We could observed gating effect and typical p-MOS property from the obtained $V_G-I_{DS}$ curve. The threshold voltage of CNT-FET is about -4.6V and transconductance is 47 nS. In the physical aspect, we could identified SWNT with phase mode of SPM which detecting phase shift by force gradient between cantilever tip and sample surface.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.339-339
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• 2012

현재 MOS 소자에 사용되고 있는 $SiO_2$ 산화막은 그 두께가 얇아짐에 따라 Gate Leakage current와 여러 가지 신뢰성 문제가 대두되고 있고, 이를 극복하고자 High-k물질을 사용하여 기존에 발생했던 Gate Leakage current와 신뢰성 문제를 해결하고자 하고 있다. 본 실험에서는 High-k(hafnium) Gate Material에 온도 변화를 주었을 때 여러 가지 전기적인 특성 변화를 보는 방향으로 연구를 진행하였다. 기본적인 P-Type Si기판을 가지고, 그 위에 있는 자연적으로 형성된 산화막을 제거한 후 Hafnium Gate Oxide를 Atomic Layer Deposition (ALD)를 이용하여 증착하고, Aluminium을 전극으로 하는 MOS-Cap 구조를 제작한 후 FGA 공정을 진행하였다. 마지막으로 $300^{\circ}C$, $450^{\circ}C$로 30분정도씩 Annealing을 하여, 온도 조건이 다른 3가지 종류의 샘플을 준비하였다. 3가지 샘플에 대해서 각각 I-V (Gate Leakage Current), C-V (Mobile Charge), Interface State Density를 분석하였다. 그 결과 Annealing 온도가 올라가면 Leakage Current와 Dit(Interface State Density)는 감소하고, Mobile Charge가 증가하는 것을 확인할 수가 있었다. 본 연구는 향후 High-k 물질에 대한 공정 과정에서의 다양한 열처리에 따른 전기적 특성의 변화 대한 정보를 제시하여, 향후 공정 과정의 열처리에 대한 방향을 잡는데 도움이 될 것이라 판단된다.

• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• Transactions on Electrical and Electronic Materials
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• 제8권3호
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• pp.139-142
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• 2007

Organic field-effect transistor (FET) based on a copper Phthalocyanine (CuPc) material as an active layer and a $SiO_2$ as a gate insulator were fabricated and analyzed. We measured the typical FET characteristics of CuPc in air. The electrical characteristics of the CuPc FET device were analyzed by a Maxwell-Wagner model. The Maxwell-Wagner model employed in analyzing double-layer dielectric system was helpful to explain the C-V and I-V characteristics of the FET device. In order to further clarity the channel formation of the CuPc FET, optical second harmonic generation (SHG) measurement was also employed. Interestingly, SHG modulation was not observed for the CuPc FET. This result indicates that the accumulation of charge from bulk CuPc makes a significant contribution.

• 한국재료학회지
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• 제12권3호
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• pp.211-214
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• 2002

Properties of 52/48 PZT films with various thicknesses for piezoelectric micro-electro mechanical systems (MEMS) devices fabricated by multi-coating method on $Pt(3500{\AA})/Ti(400{\AA})/SiO_2(3000{\AA})/Si$(525$\mu\textrm{m}$) substrates were investigated. PZT films were deposited by spin-coating process at 3500 rpm for 30 sec, followed by pyrolysis at 45$0^{\circ}C$ for 10 min producing the thickness of about 120nm. These processes were repeated 4, 8, 12, 16 and 20 times in order to have various thicknesses, respectively. Finally, they were crystallized at $650^{\circ}C$ for 30 min. All thick PZT films showed dense and homogeneous surface microstructures. Thick PZT films showed crystalline structures of random orientations with increasing thickness. Dielectric constants of thick PZT films were increased with increasing film thickness and reached 800 at 100kHz for 2.3$\mu\textrm{m}$ thick PZT film. $P_r\; and\; E_c$ of 2.3$\mu\textrm{m}$ thick PZT films were about 20$\mu$C/$\textrm{cm}^2$ and 63kV/cm. Depth profile analysis by Auger Electron Spectroscopy (AES) of 4800 $\AA$ thick PZT film showed the formation of the perovskite phase on Pt layer by Pb diffusion behavior. It was considered that Pb-Pt intermediate layer promoted PZT (111) columnar structures.

• 한국통신학회논문지
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• 제25권9B호
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• pp.1527-1533
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• 2000

MIS(도체-부도체-반도체) 구조로된 전송선로를 해석하기 위하여 기본적으로 특성임피던스와 전파상수의 추출에 기초한 일반적인 특성화 절차가 사용된다. 본논문에서는 Si와 Si02층 사이에 0전위를 가진 도체를 일정한 간격의 주기적인 배열로 고안된 새로운 모델의 MIS구조에 대한 유한차분법을 이용한 해석방법을 제안한다. 특히 전송선로에 대한 유전체의 영향을 줄이기 위하여 0전위를 가진 주기적인 결합의 도체로 이루어진 구조가 시간영역의 신호를 통해 시험된다. Quality factor 뿐만아니라 주파수 의존적인 추출된 전송선로 파라미터와 등가회로 파라미터가 주파수 및 0전위 도체 간격의 함수로서 나타내진다. 특히 전송선로의 Quality factor가 특성임피던스 및 유효유전 상수의 큰 변화없이 개선될수 있음을 볼 수 있다.