• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
• /
• pp.201-202
• /
• 2005

The electrical characteristics of high-voltage LDMOSFET (Lateral Double-diffused MOSFET) fabricated by a CMOS technology were investigated depending on the process and design parameters. The off-state breakdown voltages of n-channel LDMOSFETs were linearly increased with increasing to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times10^{13}/cm^2$ to $1.0\times10^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times, however, the on-resistance was also increased about 76%. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region.

• 한국재료학회지
• /
• 제26권6호
• /
• pp.347-352
• /
• 2016

ZnO with wurtzite structure has a wide band gap of 3.37 eV. Because ZnO has a direct band gap and a large exciton binding energy, it has higher optical efficiency and thermal stability than the GaN material of blue light emitting devices. To fabricate ZnO devices with optical and thermal advantages, n-type and p-type doping are needed. Many research groups have devoted themselves to fabricating stable p-type ZnO. In this study, $As^+$ ion was implanted using an ion implanter to fabricate p-type ZnO. After the ion implant, rapid thermal annealing (RTA) was conducted to activate the arsenic dopants. First, the structural and optical properties of the ZnO thin films were investigated for as-grown, as-implanted, and annealed ZnO using FE-SEM, XRD, and PL, respectively. Then, the structural, optical, and electrical properties of the ZnO thin films, depending on the As ion dose variation and the RTA temperatures, were analyzed using the same methods. In our experiment, p-type ZnO thin films with a hole concentration of $1.263{\times}10^{18}cm^{-3}$ were obtained when the dose of $5{\times}10^{14}$ As $ions/cm^2$ was implanted and the RTA was conducted at $850^{\circ}C$ for 1 min.

• 한국진공학회지
• /
• 제4권S2호
• /
• pp.90-94
• /
• 1995

Defects introduced by Si, Ge preamorphization and their effects on the dopant diffusion and electrical characteristics. Good crystalline quality are obtained after the annealing of Ge ion double implanted samples. The defect clusters under the a/c interface are expected to extend up to the deep in the Si ion implanted samples. The dislocation loops near the junction absorb the interstitial Si atoms resolving from the defect cluster and result in the prevention of enhanced boron diffusion near the tail region of boron profile and show good reverse current charactristics.

• Transactions on Electrical and Electronic Materials
• /
• 제14권5호
• /
• pp.250-253
• /
• 2013

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of $N_2$ ion implantation ($N_2$ I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage ($V_{\tau}$) of 0.13 V, and a higher $g_{m.max}$ of 18.6 ${\mu}A/V$ and mobility of 27.02 $cm^2/Vs$ than the conventional and $N_2$ I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and $N_2$ I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

• 한국표면공학회지
• /
• 제41권6호
• /
• pp.292-300
• /
• 2008

Dental implant system is composed of abutment, abutment screw and implant fixture connected with screw. The problems of loosening/tightening and stability of abutment screw depend on surface characteristics, like a surface roughness, coating materials and friction resistance and so on. For this reason, surface treatment of abutment screw has been remained research problem in prosthodontics. The purpose of this study was to investigate the stability of TiN and WC coated dental abutment screw, abutment screw was used, respectively, for experiment. For improving the surface characteristics, TiN and WC film coating was carried out on the abutment screw using EB-PVD and sputtering, respectively. In order to observe the coating surface of abutment screw, surfaces of specimens were characterized, using field emission scanning electron microscope(FE-SEM) and energy dispersive x-ray spectroscopy(EDS). The stability of TiN and WC coated abutment screw was evaluated by potentiodynamic, and cyclic potentiodynamic polarization method in 0.9% NaCl solution at $36.5{\pm}1^{\circ}C$. The corrosion potential of TiN coated specimen was higher than those of WC coated and non-coated abutment screw. Whereas, corrosion current density of TiN coated screws was lower than those of WC coated and non-coated abutment screw. The stability of screw decreased as following order; TiN coating, WC coating and non-coated screw. The pitting potentials of TiN and WC coated specimens were higher than that of non-coated abutment screw, but repassivation potential of WC coated specimen was lower than those of TiN coated and non-coated abutment screws due to breakdown of coated film. The degree of local ion dissolution on the surface increased in the order of TiN coated, non-coated and WC coated screws.

• 한국전기전자재료학회논문지
• /
• 제17권9호
• /
• pp.911-915
• /
• 2004

In this study, the electrical characteristics of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated depending on its process and design parameter. In order to verify the experimental data, two-dimensional device simulation was carried out simultaneously. The off- state breakdown voltages of n-channel LDMOSFETs were increased nearly in proportional to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times{10}^{13}/cm^2$ to $1.0\times{10}^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times. The on-resistance was also increased about 76 %. From 2-D simulation, the increase in the breakdown voltage was attributed to a reduction in the maximum electric field of LDMOS imolanted with low dose as well as to a shift toward n+ drain region. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region. The experimental and design data of these high-voltage LDMOS devices can widely applied to design smart power ICs with low-voltage CMOS control and high-voltage driving circuits on the same chip.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1990년도 추계학술대회 논문집
• /
• pp.88-90
• /
• 1990

In this study, PN junction solar cell and P$\^$+/-N-N$\^$+/ BSF solar cell, using N-type(111), 10$\^$16/[atoms/cm$\^$-3/] wafer, were fabricated applying that ion implant method whose dose are 1E14, 1E15, 3E15 and its acceleration energy is 50Key, 100Key respectively. The impurity concentration of two types of front-side are 10$\^$18/[atoms/cm$\^$-3/] and back-side concentration for BSF solar cell is 10$\^$17/[atoms/cm$\^$-3/]. As a result of comparison for 2 typical types of cells out of various fabricated samples, open circuit voltage (Voc), short circuit current(Isc) of BSF solar cell are larger than those of PN solar cell by 48[%], 14[%]. Considering that the efficiency of BSF cell is 2.5[%] as well as PN solar cell's is 7.5[%], 10.0[%] of efficiency improvement effect can be obtained from BSF solar cell. Futhermore, in consequence of front-side impurity concentration change from 10$\^$17/[atoms/cm$\^$-3] to 10$\^$20/[atoms/cm$\^$-3/] alternately, the most ideal result can be expected when it is 10$\^$18/[atoms/cm$\^$-3/].

• 한국위성정보통신학회논문지
• /
• 제8권2호
• /
• pp.36-43
• /
• 2013

본 논문에서는 고전압에서 동작하는 DDIC(display driver IC) 칩의 정전기 보호소자로 사용되는 GG_EDNMOS 소자의 고전류 특성 및 더블 스냅백 메커니즘이 분석되었다. 이온주입 조건을 달리하는 매트릭스 조합에 의한 수차례의 2차원 시뮬레이션 및 TLP 특성 데이타를 비교한 결과, BJT 트리거링 후에 더블 스냅백 현상이 나타났으나 웰(well) 및 드리프트(drift) 이온주입 조건을 적절히 조절함으로써 안정적인 ESD 보호성능을 얻을 수 있었다. 즉, 최적의 백그라운드 캐리어 밀도를 얻는 것이 고전압 동작용 정전기보호소자의 고전류 특성에 매우 중요한 영향을 주는 임계인자(critical factor)임을 알 수 있었다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
• /
• pp.155.2-155.2
• /
• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• 대한전자공학회논문지
• /
• 제16권4호
• /
• pp.36-46
• /
• 1979

본 연구에서는 N -채널 실리콘 게이트 제작기술에 의하여 일련의 크기를 가지는 커페시터와 트렌지스터들이 제작되었다. 그 결과 다양한 이온 주입 조걸, 즉 B 의 경우 에너지 30keV∼60keV와 도오스 3 × 10 ~ 5 × 10 개/㎠ 그리고 P 의 경우 에너지 1001keV∼ 175keV와 4 ×10 ~ 7×11개/㎠ 도오스 영역에서 이들에 대한 D.C. 인자들의 측정치들이 이론적인 계산치들과 비상, 분석되어 있다. 이 D.C. 인자들에는 threshold전압, 공핍층의 폭, 게이트 산화물 두께, 표면상태, 가동 하전입자 밀도, 전자의 이동도 그리고 마지막으로 누설전류가 있는데, 이중 실제 MOS의 제작에 있어서 특허 중요한 threshold전압에 있어서는, 커어브트레이서와 C - V plot을 통하여 측정된 값들이 실제 재산에서 이용된 SUPREM II 컴퓨우터 프로그램에 의한 결과와 훌륭히 접근하고 있다. 그 밖에 여기나온 D.C.인자들 중에서 도오핑 수준은 기판의 역 게이트 바이어스에서 threshold전압들로 부터 계산된 것이고, 역전도는 정의된 subthreshold 기울기로 부터 추산된 것임을 밝혀 둔다. 마지막으로 이와같은 D. C. 시험 결과들을 종합적으로 평가해 볼 때 만들어진 커페시터와 트렌지스터들이 N -채널 MOS I. C. 기억소자용으로 적합함을 보여주고 있다.