Radio data system is a next-generation broadcasting system of digital information communication which multiplexes the digital data into the FM stereo signal in VHF/FM band and provides important and convenient service features. And radio data are composed of groups which are divided into 4 blocks with information word and check word. In this paper, radio data receiver is developed which recovers and process radio data to provide services. Then we confirm that 7dB SNR is required to be 10S0-5TBER of demodulation. Deconding process of shortened-cyclic-decoder has been simulated by computer. Also, the time-compression (by 16 times) method has been adopted for the RDS features post-processing. Via the error probability calculation, simulation and experimentation, the developed receiver system is proved to satisfy the system specification of EBU and implemented by general logic gates and analog circuits.

A new line code design technique based on the BUDA(Binary Unit DSV and ASV) concept is introduced. The new line code called MB34 and designed by this new technique is of the minimum bandwidth, dc-free, and runlength limited. To confirm the performance of the new code, its power spectrum and eye pattern are obtained, wherein spectral nulls at dc(f=0) and Nyguist frequency (f=1/2Ts) are clearly identified. It is also discussed how the transmission errors can be detected by monitoring the DSV, the ASV, and the runlength.

Given a protocol specification, the task of testing whether an implementation conforms to the specification is called conformance testing. In this paper, the design and implementation of the protocol conformance test system using LAN on heterogeneous systems is descreibed. The test sequence used in this test system is generated using an algorithm on the basis of multiple UIO. The usability of this test system as an application was confirmed by performing the conformance test on the CCITT No.7 TCAP(transaction capabilities application part), implemented by ISDN Laboratory, Korea University in 1990.

This paper describes a new phase-difference detection method and the associate process algorithm for calculating the mean value of phase difference detected and OVCXO control value and for monitoring and controlling the DP-PLL operation status to be used in the design of a high-frequency DP-PLL. Through the experiments of DP-PLL implemented with 16-bit processor, memories, pheriperals and OVCXO to eraluate the suggested method and algorithm, it is shown that a remarkable improvement in PLL function such as phase detection, and reference clock tracing capability, jitter absorbability and frequency stability compared with other existing DP-PLL synchronization device is achieved.

This paper shows a new relational formula of multiplexing gain versus variable input bit rates useful for designing Nx1 ATM(Asynchronous Transfer Mode) multiplexer which mixes several asynchronous bit streams with different transmission rates. The relation between multiplexing gain and input bit stream speeds is derived from the occupied mean lenght(the width per unit time) of cells and the occupation probability of the number of cells at an arbitrary instant when the rates of the periodic cell strams change randomly. And the relation between multiplexing gain and variable bit rates from different number of input bit streams is analyzed accordingly. Under the condition of unlimited multiplexing speed, the more number of input bit streams increases, the bigger the multiplexing gain becomes. While for the case which restricts the multiplexing speed to a limited value, the multiplexing gain becomes smaller contrarily as the number of input bit streams continues too invrease beyond a boundary value. It is shown that for designing an ATM multiplexer according to the latter case, the combination of input bit streams should be determined such as its total bit rate is lower thean, but most apprpaximate to, the multiplexed output speed. Also the general formula evaluating the most significant parameters which should be needed to design the multiplexer is derived.

The characteristics of traveling-wave electrodes for high-frequency electroptic integrated devices are described from the view point of improvement of phase-matching based on the conformal mapping method. Specific calculations of the characteristic impedance, effective microwave index, and eletrode loss for asymmetric coplanar strip(ACPS) and coplanar waveguide(CPW) electrode structures are presented as a function of the geometric electrode parameters including the electrode thickness and buffer layer thickness. 5-10(x10S0-6Tm) thick Au-ACPS electrodes were successfully fabricated by electroplating and ECR etcher. The improvement of modulation bandwidth can be theoretically observed from the combination of electrode and buffer layer thickness.

We Have investigated the properties of the titanium nitrite films widely used in VLSI devices as diffusion barrier in Al-based metallization. TiN films were formed by reactive sputtering from Ti target in Ar-N$_2$ mixtures, varying deposition parameters such as N$_2$ partial pressure, substrate temperature, power, and total pressure. All the samples received the heat treatment at 45$0^{\circ}C$ for 30 min. The resulting films are characterized by mechanical stylus($\alpha$-step), x-ray diffraction(XRD), scanning electron microscopy(SEM), and four point probe method. The Tin film properties strongly depend on the deposition condition. The stoichiometry and Ti deposition rate are critically affected by nitrogen partial pressure, and the resistivity, in particular, is dependent on both the substrate temperature and sputtering power.

This paper is analyzed the charge trapping and electrical properties of 0(Oxide), NO(Nitrided oxide) and ONO(Reoxidized nitrided oxide) as dielectric films in MIS structures. We have processed bottom oxide and top oxide by the thermal method, and nitride(Si$_{3}N_{4}$) by the LPCVD(Low Pressure Chemical Vapor Deposition) method on P-type(100) Silicon wafer. We have studied the charge trapping properties of the dielectrics by using a computer controlled DLTS system. All of the dielectric films are shown peak nearly at 300K. Those are bulk traps. Many trap densities which is detected in NO films, but traps. Many trap densities which is detected in NO films. Varing the nitride thickness, the trap densities of thinner nitride is decreased than the thicker nitride. Finally we have found that trap densities of ONO films is affected by nitride thickness.

Deposition properties and film characteristics of Remote PECVD silicon dioxide were investigated. Using $N_{2}O/SiH_{4}$, the effects of changing the process conditions` the pressure, the substrate temperature, and the gas mixing ration, on the film quality were observed. A comparison of film qualites of the Remote PECVD SiO$_2$ with that of a Direct PECVD SiO$_2$ was made. The experimental results show that the Remote PECVD SiO$_2$ has better electrical, physical, and annealing properties than the Direct PECVD oxide.

According to increasing the doping concentration in p-n junction, a tunneling current through trap as well as SRH(Shockley-Read-Hall) generation-recombination current in depletion region occurs. It is the tunneling current that is a dominant current at the forward bias. In this paper, the new tunneling-recombination equation is derived. The thermal generation-recombination current and tunneling current though trap can be easily calculated at the same time because this equation has the same form as the SRH generation-recombination equation. For the validity of this equation, 2 kind of samples are simulated. The one is $n^{+}$-p junction device fabricated with MCT(Mercury Cadmium Telluride, mole fraction=0.29), the other Si n$^{+}-p^{+}$ junction. From the results for MCT $n^{+}$-p junction device and comparing the simulated and expermental I-V characteristics for Si n$^{+}-p^{+}$ junction, it is shown that this equation is a good description for tunneling through trap and thermal generation-recombination current calculation.

To improve the characteristics of sub$\mu$m short channel MOSFET device, a new device having the convex structure is proposed. This device has 3-dimensionally expandable channel length according to the vertical etched silicon height. For the purpose of comparing the DC and AC characteristics, planar device is also fabricated. Comparing the channel length, the convex device with 0.4$\mu$m silicon height is larger about 0.56$\mu$m in NMOS and 0.78$\mu$m in PMOS than planar devices. DC characteristics, such as threshold voltage, operational current, substrate current and breakdown voltage are compared together with AC characteristics using the ring oscillator inverter delay. Also process and device simulation are performed and the differences between convex and pranaldevice are also compared.

IIM(Implantation Into Metal) process usning Co silicides has been investigated to obtain ultra-shallow junctions less than 0.1$\mu$m. Rapid Thermal Annealing using halogen lamps was employed to form CoSi$_2$ and junctions simultaneously.. Resistivities of CoSi$_2$ were 13-17$\mu$ $\Omega$-cm. CoSi$_2$/p$^{+}$/Si and CoSi$_2$/n$^{+}$/Si junction were formed by diffusion of B and As, respectively, from Co film. It was found out that B and As were severely lost by the evaporation during high temperature annealing Therefore SiO$_2$ capping layers were introduced to prevent the evaporation of the implanted dopants from the films. Investigation of the behavior of dopants with respect to annealing time revealed that increasing the annealing time enhanced the diffusion of dopants into Si from CoSi$_2$.

First, the coupling faults of semiconductor memory are classified in detail. The chained coupling fault is introduced and defined, which results from sequential influencing of the coupling effects among memory cells, and its mapping relation is described. The linked coupling fault and its order are defined. Second, the deterministic “Algorithm GA” is proposed, which detects stuack-at faults, transition faults, address decoder faults, unlinked 2-coupling faults, and unlinked chained coupling faults. The time complexity and the fault coverage are improved in this algorithm. Third, it is proved that the march test of an address sequence can detect 97.796% of the linked 2-coupling faults with order 2. The deterministic “Algorithm NA” proposed can detect to the limit. The time complexity and the fault coverage are improved in this algorithm.