In this paper, we evaluated the mean acquisition time and it's variance of the rapid synchronization system using the DMF(Digital Matched Filter) under the DS/CDMA system which uses the long period PN code. And we implemented the synchronization system that satisfies the specification demanded by the proposed EIA/TIA Interim Standard of Qualcomm Company. We showed that the state of the PN spreading code was estimated using the DMF(Digital Matched Filter) and then exact and fast chip synchronization could be achieved by the early-late tracking loop in the multiple channel environment. And we suggested the possibility that this synchronization system could be useful in the emerging digital cellular DS/CDMA system.

A new dual-mode algorithm for blind equalization of quadrature amplitude modulation (QAM) signals is proposed. To solve the problem that the constant modulus algorithm (CMA) converges to the constellation with the arbitrary phase rotation, with the modification of the CMA, the proposed algorithm accomplishes blind equalization and carrier phase recovery simultaneously. In addition, the dual-mode algorithm combining the modified constant modulus algorithm (MCMA) with decision-directed (DD) algorithm achieves the performance enhancement of blind convergence speed and steady-state residual ISI. So we can refer the proposed algorithm to as a scheme for joint blind equalization and carrier phase recovery. Simulation results for i.i.d. input signals confirm that the dual-mode algorithm results in faster convergence speed, samller residual ISI, and better carrier phase recovery than those of the CMA and DD algorithm without any significant increase in computational complexity.

A new class of DC-error correcting codes based on convolutional codes is proposed with its performance analysis. The proposed codes can be encoded and decoded using the conventional convolutional encoders and decoders with slight modifications. And the codes have null point at DC and capable of correcting errors. The DC-free error correcting codes are especially well suited for applications in high-speed channels.

In this paper, the relationship between k consecutive outputs of the conventional differential detector and output of differential detector with k-symbol periods delay for differential MSK and GMSK systems is investigated. It is hown that there exists periodity in modulo-2 sum and product of k successive outputs of the conventional differential detector with the output of a detector with k-symbol periods delay circuit. This relationships are used to achieve performance gains over conventional differential detection. The error rate performance of the method is carried out by computer simulation and performance improvement is achieved for differential MSK and GMSK systems.

Token bus protocols have been sidely accepted for Medium Access Control (MAC) in real-time networks such as those used in factory automation, distributed process control, nuclear power plant, aircraft and spacecraft. Token bus protocols provide timer-controlled priority mechanism, which offers multiple level of privilege of medium access to different type of traffic. This paper presents and approximate analytical model for the evaluation of variance of waiting time in the time-controlled proiority scheme of token bus protocols. Token bus system is assumed to be operated with singe-service discipline which is the practical case of real-time networks such as those used in distributed process control and factory automations. The approximate analytical model is validated by comparison with the simulation resuls.

We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

As a Basic study to implement a wide-band photonic switching sysetm, we proposed a scheme of free-space-division-multiplexed photonic switching based on a holographic interconnectio method and carried out simple experiments on it. First, we recorded holgraphic interconnection element array for nonblocking optical interconnections. Just a single stage of the array realizes full optical interconnections between NN${\times}$NN input prots and NN${\times}$NN output ports in 3-D space. Next, in reading of the array for optical internnections, we showed that the zeroth-order diffacted beam could be eliminated in the output port by introducing a right angle prism. The elimination of the zeroth-order diffracted beam reduces optical noise in the output ports and provides conveniences of interconnection control in our scheme. Finally, from the experiments on ON-OFF switching of the optical interconnection paths one by one using a spatial (display of the liquid crystal telecision), we showed the feasibility of photonic wsitching based on the holographic interconnection method. We also estimated approximately the maximum interconnectio scale that can be realized without difficulty with current optical devices.

The usual approach for desinging a fast multiplier involves finding a way to quickly add up all the partial products, based on parital product recoding scheme and carry-save addition. This paper describes theoretical medels for area and time complexities of Multibit Reconding Paralle Multiplier (MRPM), which is a generalization of the modified Booth recoding scheme. Based on the proposed models, time performance, hardware requirements and area-time efficiency are analyzed in order to determine optimal recoding size for very large scale integration (VLSI) realization of the MRPM. Some simulation results show that the MRPM with large multiplier and multiplicand size has optimal area-time efficiency at the recoding size of 4-bit.

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

There are many testable design techniques, among which Scan path and BIST techniques are mainly used. In this paper, the increase of design effectiveness is discussed, when these techniques are applied to the practical implementation of chips. The following techniques are presented : 1) Blocks are commonly used to reduce test time without hardware increase, 2) MUX is used to implement the shortest Scan path, 3) Scan register is used which controls and/or observes several blocks to avoid the increase of hardware.