Transactions of the Korean Society of Machine Tool Engineers (한국공작기계학회논문집)

The Korean Society of Manufacturing Technology Engineers (한국생산제조학회)
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The Stress Analysis of Semiconductor Package

반도체 패키지의 응력 해석

  • 이정익 (인하공업전문대학 기계설계과)
  • Published : 2008.06.15
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Abstract

In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).

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References

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