• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.43-50
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• 1998

The purpose of the paper is to protect the damage of plastic IC package with searching the cause of the fracture due to the delamination and crack when the encapsulant of plastic IC package is on viscoelastic behavior with the effect of creep on high temperature, The model for analysis is the plastic SOJ package with dimpled diepad in the IR soldering process of surface mounting technology. The risk of delamination with calculating the distribution of viscoelastic thermal stress in the package without the crack in the surface mounting process is checked. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance against fracture in thermal loading with calculating C (t)-integrals according to the change of the design. The optimum design to depress the delamination and crack is presented.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.1
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• pp.51-59
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• 1998

The purposes of the paper are to consider the failure phenomenon based on delamination and crack when the encapsulant of plastic IC package under hygrothermal loading in the IR soldering process is on elastic and viscoelastic behavior due to the temperature and to show the optimum design using fracture mechanics. The model for analysis is the plastic SOJ package with a dimpled diepad. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance to fracture by calculating J-integrals in low temperature and C(t)-integrals in high temperature with the change of the design under hygrothermal loading. The optimum design to depress the delamination and crack in the plastic IC package is presented.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.4
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• pp.1347-1355
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• 1996

The purpose of this paper is to evaluate the delamination and fracture integrity of the IC plastic package under hygrothermal loading by stress analysis and fracture mechanics approaches. The plastic SOJ package with a dimpled diepad under the reflow slodering process of IR heating type is considered. On the package without a crack, the stress variation according to the change of the design variables such as the material and shape of the package is calculated and the possibility of delamination is considered. For the model fully delaminated between the chip and diepad, J-integrals are calculated for the various design variables and the fracture integrity is discussed. From the results, optimal design values of variables to prevent the delamination and fracture of IC package are obtained. In this study, FDM program to obtain the vapor pressure from the content of moisture absorbed into the package is developed.

• Journal of the Korean Society for Nondestructive Testing
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• v.12 no.4
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• pp.18-25
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• 1993

This paper is to aim the microdefect evaluation of If package into a quantitative from NDI's image processing of ultrasonic wave. (1) Automatically repeated discrimination analysis method can be devided in the category of all kind of defects on IC package, and also can be possible to have a sampling of partial delamination. (2) It is possible that the information of edge section in silicon chip surrounding can be extractor by the partial image processing of IC package. Also, the crack detection is possible between the resin part and lead frame.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.389-392
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• 1999

It is essential to estimate an effective inductance in a ground plane of muliti-layer IC package system in order to determine the simultaneous switching noise of the package. A new method to estimate the effective ground inductance in multi-layer IC package is presented. With the estimated ground plane inductance values, maximum switching noise variations according to the number of simultaneously switching drivers are investigated by developing a new SSN model. These results are verified by performing HSPICE simulation with the 0.35${\mu}{\textrm}{m}$ CMOS technology.

• Journal of Mechanical Science and Technology
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• v.18 no.3
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• pp.357-369
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• 2004

The purposes of the paper are to analyze the fracture phenomenon by delamination and cracking when the encapsulant of plastic IC package with polyimide coating shows viscoelastic behavior under hygrothermal loading in the IR soldering process and to suggest more reliable design conditions by the approaches of stress analysis and fracture mechanics. The model is the plastic SOJ package with the polyimide coating surrounding chip and dimpled diepad. On the package without cracks, the optimum position and thickness of polyimide coating to decrease the maximum differences of strains at the bonding surfaces of parts of the package are studied. For the model delaminated fully between the chip and the dimpled diepad, C(t)-integral values are calculated for the various design variables. Finally, the optimal values of design variables to depress the delamination and crack growth in the plastic IC package are obtained.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1141-1144
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• 1998

A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the $0.35\mu\textrm{m}$ CMOS model parameters.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.6
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• pp.709-716
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• 2004

In order to prevent the interface delamination of an plastic IC package in the infrared (IR) soldering process, we tried to reduce stress by parameterization, sensitivity analysis and unconstraint optimization. The design variables of dimensions and material properties are determined among all the possible variables from the parametric study. Their optimized values are determined by applying the unconstraint optimization to the parameterized IC package. The maximum von-Mises stress value decreases greatly by optimum design.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.133-136
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• 2001

A new package design method to reduce resonance effect due to an IC package is represented. Frequency-variant circuit model of the power/ground plane was developed to accurately reflect the resonance. The circuit model is benchmarked with a full wave simulation, thereby verifying its accuracy. Then it was shown that the proposed technique can efficiently reduce the resonance due to the IC package.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.3-7
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• 2000

In summary, a fundamentally new paradigm called System-on-Package could potentially become a complementary alternative to System-on-Chip, thus providing a balanced set of system-level functions between the semiconductor IC and single component package beyond the year 2007. The concurrent engineering and optimization of IC and package could overcome the fundamental IC issues presented above.