• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.139-144
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• 2019

For recent decades, Non-volatile Memory (NVM) technologies have been drawing a high attention both in industry and academia due to its high density and short latency comparable to that of DRAM. However, NVM devices has write endurance problem and thus the current data structures that have been built around DRAM-specific features including unlimited program cycles is inadequate for NVM, reducing the device lifetime significantly. In this paper, we revisit a red-black tree extensively adopted for data indexing across a wide range of applications, and make it to better fit for NVM. Specifically, we observe that the conventional red-black tree wears out the specific location of memory because of its rebalancing operation to ensure fast access time over a whole dataset. However, this rebalancing operation frequently updates the long-lived nodes, which leads to the skewed wear out across the NVM cells. To resolve this problem, we present a new swapping wear-leveling red-black tree that periodically moves data in the worn-out node into the young node. The performance study with real-world traces demonstrates the proposed red-black tree reduces the standard deviation of the write count across nodes by up to 12.5%.

• Journal of KIISE
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• v.42 no.8
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• pp.947-953
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• 2015

PRAM is being considered as a potential successor to DRAM because of its characteristics such as byte-addressability, non-volatility, and high density. To gain its benefits, buffer cache replacement algorithm based on PRAM has been actively studied. However, most of the previous studies on buffer cache replacement algorithm limitedly exploit the byte-level performance of PRAM by focusing its limited lifetime and slower access latency compared to DRAM. In this paper, we propose a novel buffer cache replacement algorithm that fully considers the byte-level performance of PRAM and the performance of secondary storage. To take advantage of small size write on PRAM, proposed scheme keeps pages, which are frequently accessed with a small size write, on PRAM and allows the selective page migration from DRAM to PRAM. As a result, our scheme significantly reduces the number of PRAM writes. Our experimental results indicate for real workloads that our scheme reduces the number of PRAM writes by up to 92% and improves its performance by up to 62% compared to CLOCK.

• The Journal of the Korea Contents Association
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• v.21 no.7
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• pp.157-163
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• 2021

A single write operation in a file system can modify multiple data, but these changes in the file system are not atomically written to disk. Thus, for the consistency of the file system, conventional journaling guarantees crash consistency instead of sacrificing the system performance. It is known that using non-volatile memory as a journal space can alleviate performance degradation due to low latency and byte-level accessibility of non-volatile memory. However, none of the journaling techniques considering non-volatile memory provide scalability. In this paper, journal space on non-volatile memory is divided into multiple regions for scalable journaling, thus dispersing concentrated operations in one region. Second, the journal area-specific operator structure is used to accelerate data write operations to storage devices. We apply the proposed technique to JFS to evaluate it on multi-core servers equipped with high-performance storage devices. The evaluation results show that the proposed technique performs better than the existing technique of the NVM-based journaling file system.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.54-62
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• 2010

Inverted index structures have become the most efficient data structure for high performance indexing of large text collections, especially online index maintenance, In-Place and merge-based index structures are the two main competing strategies for index construction in dynamic search environments. In the above-mentioned two strategies, a contiguity of posting information is the mainstay of design for online index maintenance and query time. Whereas with the emergence of new storage device(SSD, SCRAM), those do not consider a contiguity of posting information in the design of index structures because of its superiority such as low access latency and I/O throughput speeds. However, SSD(Solid State Drive) is not well suited for traditional inverted structures due to the poor random write throughput in practical systems. In this paper, we propose the new efficient online index structure(SPM) for SSD that significantly reduces the query time and improves the index maintenance performance.

• The KIPS Transactions:PartA
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• v.18A no.4
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• pp.135-142
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• 2011

This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.68-76
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• 2015

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• ETRI Journal
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• v.39 no.6
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• pp.820-831
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• 2017

File systems and applications try to implement their own update protocols to guarantee data consistency, which is one of the most crucial aspects of computing systems. However, we found that the storage devices are substantially under-utilized when preserving data consistency because they generate massive storage write traffic with many disk cache flush operations and force-unit-access (FUA) commands. In this paper, we present DJFS (Delta-Journaling File System) that provides both a high level of performance and data consistency for different applications. We made three technical contributions to achieve our goal. First, to remove all storage accesses with disk cache flush operations and FUA commands, DJFS uses small-sized NVRAM for a file system journal. Second, to reduce the access latency and space requirements of NVRAM, DJFS attempts to journal compress the differences in the modified blocks. Finally, to relieve explicit checkpointing overhead, DJFS aggressively reflects the checkpoint transactions to file system area in the unit of the specified region. Our evaluation on TPC-C SQLite benchmark shows that, using our novel optimization schemes, DJFS outperforms Ext4 by up to 64.2 times with only 128 MB of NVRAM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.843-850
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• 2004

As mobile devices prevail, requests for various services using mobile devices have increased. Requests for application services that require large data space such as multimedia, game and database [1] specifically have greatly increased. However, mobile appliances have difficulty in applying various services like a wire environment, because the storage capacity of one is not enough. Therefore, research (5) which provides remote storage service for mobile appliances using iSCSI is being conducted to overcome storage space limitations in mobile appliances. But, when iSCSI is applied to mobile appliances, iSCSI I/O performance drops rapidly if a iSCSI client moves from the server to a far away position. In the case of write operation, $28\%$ reduction of I/O performance occurred when the latency of network is 64ms. This is because the iSCSI has a structural quality that is very .sensitive to delay time. In this paper, we will introduce an intermediate target server and localize iSCSI target to improve the shortcomings of iSCSI performance dropping sharply as latency increases when mobile appliances recede from a storage server.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.48-56
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• 2011

Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.