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A Buffer Cache Replacement Algorithm for Considering both Hybrid Main Memory and Storage

하이브리드 메인 메모리와 스토리지의 특성을 고려한 버퍼 캐시 교체 정책

  • 강동현 (성균관대학교 정보통신대학) ;
  • 엄영익 (성균관대학교 정보통신대학)
  • Received : 2015.02.02
  • Accepted : 2015.05.12
  • Published : 2015.08.15

Abstract

PRAM is being considered as a potential successor to DRAM because of its characteristics such as byte-addressability, non-volatility, and high density. To gain its benefits, buffer cache replacement algorithm based on PRAM has been actively studied. However, most of the previous studies on buffer cache replacement algorithm limitedly exploit the byte-level performance of PRAM by focusing its limited lifetime and slower access latency compared to DRAM. In this paper, we propose a novel buffer cache replacement algorithm that fully considers the byte-level performance of PRAM and the performance of secondary storage. To take advantage of small size write on PRAM, proposed scheme keeps pages, which are frequently accessed with a small size write, on PRAM and allows the selective page migration from DRAM to PRAM. As a result, our scheme significantly reduces the number of PRAM writes. Our experimental results indicate for real workloads that our scheme reduces the number of PRAM writes by up to 92% and improves its performance by up to 62% compared to CLOCK.

PRAM은 바이트 단위의 쓰기와 비휘발성의 특징을 모두 가지고 있으며, DRAM보다 높은 밀 집도가 기대되기 때문에 DRAM을 대체할 수 있을 것으로 예상된다. 이에, PRAM 기반의 버퍼 캐시 교체정책에 대한 연구가 활발하게 진행되고 있다. 그러나 대부분의 기존 연구는 PRAM의 수명 및 느린 쓰기 성능에만 집중함으로써 PRAM의 바이트 단위의 쓰기 성능을 제한적으로 이용한다. 이에, 본 논문에서는 PRAM의 바이트 단위의 쓰기 성능과 스토리지의 성능을 모두 고려한 새로운 버퍼 캐시 교체 정책을 제안 한다. 제안 기법은 바이트 단위의 쓰기 성능을 이용하기 위해 작은 크기의 쓰기 요청이 빈번한 페이지를 PRAM에 유지시키며 DRAM과 PRAM사이의 선택적 페이지 이동을 통해 PRAM의 쓰기 횟수를 감소시킨다. 실험 결과, 제안 기법은 CLOCK 알고리즘에 비해 최고 92%까지 PRAM의 쓰기 횟수를 감소시키고 PRAM 테스트 보드에서 최대 62%까지 수행시간을 향상시키는 것을 확인하였다.

Keywords

References

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