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Analytical Threshold Voltage Modeling of Surrounding Gate Silicon Nanowire Transistors with Different Geometries

  • Pandian, M. Karthigai;Balamurugan, N.B.
    • Journal of Electrical Engineering and Technology
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    • v.9 no.6
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    • pp.2079-2088
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    • 2014
  • In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

Application of Reverse Engineering System for Improvement of Curl Distortion in Stereolithography Process (광조형 공정시 휨에 의한 변형을 개선하기 위한 역설계 시스템의 적용)

  • Che, Woo-Seong
    • Journal of the Semiconductor & Display Technology
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    • v.8 no.4
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    • pp.7-13
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    • 2009
  • The slender device(long length and thin width) manufactured by stereolithography process suffers from large curl distortion. This paper adapts two control parameters such as a critical exposure and a penetration depth. The measurement of the test parts dimension are carried out by reverse engineering method with the optical 3-dimensional measurement equipment. We investigate how each parameter contributes to the part accuracy and estimates the optimal set of parameters which minimizes the dimensional error of the test parts. Finally, As being an the RAM slot as being an example of the slender device, the RAM slot is made with the optimal values of control parameter and the results are investigated

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On-chip ESD protection design by using short-circuited stub for RF applications (Short-Circuited Stub를 이용한 RF회로에서의 정전기 방지)

  • 박창근;염기수
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.288-292
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    • 2002
  • We propose the new type of on-chip ESD protection method for RF applications. By using the properties of RF circuits, we can use the short-circuited stub as ESD protection device in front of the DC blocking capacitor Specially, we can use short-circuited stub as the portion of the matching circuit so to reduce the and various parameters of the transmission line. This new type ESD protection method is very different from the conventional ESD protection method. With the new type ESD protection method, we remove the parasitic capacitance of ESD protection device which degrade the performance of core circuit.

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Buck converter with new driving circuit in TV poer system (TV 전원장치에서 새로운 구동 회로에 의한 buck converter)

  • 정진국
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.3
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    • pp.56-61
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    • 1996
  • In this paper, new buck converter of a TV power system is presented. First, we devised a revised driving circuit for an emitter-coupled type buck converter, by which it is possible to reduce the material cost of transformers and voltage stress of power device. Secondly, we adopted a hybrid oscillation technique. When TV system is in off-stage, initial standby power which is necessary for remote controllable TV system is supplied by self-oscillating mode. Main power which is necessry in TV system bing on state is provided by an externally triggered oscillating mode. The switching frequency is synchronized to the oscillating frequency of horizontal deflection in TV, by which we can reduce picture noises and the size of power transformer. Thirdly, a simple error amplifier is inserted to the feed-back loop to keep the output voltage constant which means pulse width modulatio mode is added in driving part of power device. Finally, we showed by experiments that our proposed converter performs well enough to be close to the theoretically predicted values.

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Design Optimization of Silicon-based Junctionless Fin-type Field-Effect Transistors for Low Standby Power Technology

  • Seo, Jae Hwa;Yuan, Heng;Kang, In Man
    • Journal of Electrical Engineering and Technology
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    • v.8 no.6
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    • pp.1497-1502
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    • 2013
  • Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ($W_{fin}$), fin height ($H_{fin}$), and doping concentration ($D_{ch}$). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.

A Study on Frequency Response of GaAs MESFET with different Temperatures (온도변화에 따른 GaAs MESFET의 주파수 특성에 관한 연구)

  • 정태오;박지홍;안형근;한득영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.550-553
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    • 2001
  • In this study, unity current gain frequency f$\_$T/ of GaAs MESFET is predicted with different temperatures up to 400 $^{\circ}C$. Temperature dependence parameters of the device including intrinsic carrier concentration n$\_$i/ effective mass, depletion width are considered to be temperature dependent. Small signal parameters such as gate-source, gate dran capacitances C$\_$gs/ C$\_$gd/ are correlated with transconductance g$\_$m/ to predict the unity current gain frequency. The extrinsic capacitance which plays an important roles in high frequency region has been taken into consideration in evaluating total capacitance by using elliptic integral through the substrate. From the results, f$\_$T/ decreases as the temperature increases due to the increase of small signal capacitances and the mobility degradation. Finally the extrinsic elements of capacitances have been proved to be critical in deciding f$\_$T/ which are originated from the design rule of the device.

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Characteristics of Transistors and Isolation as Trench Depth (트렌치 깊이에 따른 트랜지스터와 소자분리 특성)

  • 박상원;김선순;최준기;이상희;김용해;장성근;한대희;김형덕
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.911-913
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    • 1999
  • Shallow Trench Isolation (STI) has become the most promising isolation scheme for ULSI applications. The stress of STI structure is one of several factors to degrade characteristics of a device. The stress contours or STI structure vary with the trench depth. Isolation characteristics of STI was analyzed as the depth of trench varied. And transistor characteristics was compared. Isolation punch-through voltage for n$^{+}$ to pwell and p$^{+}$ to nwell increased as trench depth increased. n$^{+}$ to pwell leakage current had nothing to do with trench depth but n$^{+}$ to pwell leakage current decreased as trench depth increased. In the case of transistor characteristics, short channel effect was independent on trench depth and inverse narrow width effect was greater for deeper trenches. Therefore in order to achieve stable device, it is important to minimize stress by optimizing trench depth.

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A Study on the TFT Fabrication Using Anodized Aluminium Oxide Film (양극산화 알루미늄피막을 이용한 박막트랜지스터의 구성에 관한 연구)

  • 김봉흡;홍창희
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.31 no.9
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    • pp.74-81
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    • 1982
  • One of the stable thin film transistor fabricated by cadmium suifide with the anodized aluminium oxide as gate material. The principle of the operation for the device is based on the control mechanism of injected majority carricrs to the wide band gap semiconductor, that is cadmium sulfide, by means of the function of the gate control. The fabricated device constructed by evaporating CdS layer in the form of microcrystalline on the oxided thin film characterized by ea, 80 as voltage amplification factor, 1/100 mho as transconductance, 8 kohm as dynamic output resistance, furthermore gain band width products is about 15 MHz.

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3-D Characterizing Analysis of Buried-Channel MOSFETs (매몰공핍형 MOS 트랜지스터의 3차원 특성 분석)

  • Kim, M. H.
    • Proceedings of the Optical Society of Korea Conference
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    • 2000.08a
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    • pp.162-163
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    • 2000
  • We have observed the short-channel effect, narrow-channel effect and small-geometry effect in terms of a variation of the threshold voltage. For a short-channel effect the threshold voltage was largely determined by the DIBL effect which stimulates more carrier injection in the channel by reducing the potential barrier between the source and channel. The effect becomes more significant for a shorter-channel device. However, the potential, field and current density distributions in the channel along the transverse direction showed a better uniformity for shorter-channel devices under the same voltage conditions. The uniformity of the current density distribution near the drain on the potential minimum point becomes worse with increasing the drain voltage due to the enhanced DIBL effect. This means that considerations for channel-width effect should be given due to the variation of the channel distributions for short-channel devices. For CCDs which are always operated at a pinch-off state the channel uniformity thus becomes significant since they often use a device structure with a channel length of > 4 ${\mu}{\textrm}{m}$ and a very high drain (or diffusion) voltage. (omitted)

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A Study on the Collapse Characteristics of Hat-shaped Members with Spot Welding under Axial Compression(II) (모자형 단면 점용접부재의 축방향 압궤특성에 관한 연구(II))

  • 차천석;양인영
    • Journal of the Korean Society for Precision Engineering
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    • v.17 no.5
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    • pp.195-201
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    • 2000
  • The fundamental spot welded sections of automobiles (hat-shaped and double hat-shaped sections) absorb most of the energy in a front impact collision. The sections of various thickness, shape and weld width on the flange lave been tested on axial impact crush load (Mass 40kg, Velocity 7.19m/sec) using a vertical air pressure crash est device Characteristics of impact collapse have been reviewed and a structure of optimal energy absorbing capacity is suggested.

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