• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.100-108
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• 2014

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• 한국전자파학회논문지
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• 제24권11호
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• pp.1098-1103
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• 2013

본 논문은 직렬 RLC 정합과 저항 궤환 회로를 이용하여 설계한 중심 주파수 8 GHz를 갖는 저잡음 증폭기를 제안한다. 제안하는 LNA는 입력 정합에 Degenerate inductor를 사용하여 $S_{21}$이 넓은 대역폭을 지니고 있고, 병렬로 구성된 회로를 직렬 공진 회로로 변환함으로써 입력 정합 회로를 등가회로로 축약하여 해석을 하였다. 저항 궤환 회로와 입력 RLC 정합이 모두 사용되어 제안하는 LNA는 최대 8.5 dB의 $S_{21}$(-3 dB 대역폭은 약 3.5 GHz), 잡음 지수로 5.9 dB, IIP3로는 1.6 dBm 값을 가지며, 1.2 V에서 7 mA를 소모한다.

• Journal of information and communication convergence engineering
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• 제16권4호
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• pp.252-257
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• 2018

A wideband double radiator circular disc annular monopole antenna is proposed is this work. The radiators are etched on the surfaces of two Taconic TLY-5 substrates with a circular hole cut out of each of the radiators initially at the centers of the radiators with subsequent downward displacement of the holes. The antenna is designed with a two-step feeding transformer system for impedance matching between the input power source supplied by a $50-{\Omega}$ SMA connector and the monopole radiators. The transformer system improves the bandwidth performance at higher frequencies. The proposed antenna achieves a wideband having the capability of working between 0.645 and 18.775 GHz, corresponding to a -10 dB bandwidth of 186.7% with gain ranging from 0.95 to 8.26 dBi. In comparison to other metal disc planar monopole antennas, the proposed antenna has a small total size width due to the size of the ground plane, which has a diameter 100 mm. The frequency range of the antenna provides applications in global positioning systems, mobile communications, ultra-wideband short distance communications, and wireless computer networks.

• Journal of electromagnetic engineering and science
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• 제16권4호
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• pp.241-247
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• 2016

This paper proposes the design and measurement of a 6-18 GHz front-end receiver module that has been combined into a one- channel output from a two-channel input for electronic warfare support measures (ESM) applications. This module includes a limiter, high-pass filter (HPF), power combiner, equalizer and amplifier. This paper focuses on the design aspects of reducing the noise figure (NF) and matching the phase and amplitude. The NF, linear equalizer, power divider, and HPF were considered in the design. A broadband receiver based on a combined configuration used to obtain low NF. We verify that our receiver module improves the noise figure by as much as 0.78 dB over measured data with a maximum of 5.54 dB over a 6-18 GHz bandwidth; the difference value of phase matching is within $7^{\circ}$ between ports.

• ETRI Journal
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• 제34권4호
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• pp.485-491
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• 2012

In this paper, the implementations of a $0.1{\mu}m$ gallium arsenide (GaAs) pseudomorphic high electron mobility transistor process for a low noise amplifier (LNA), a subharmonically pumped (SHP) mixer, and a single-chip receiver for 70/80 GHz point-to-point communications are presented. To obtain high-gain performance and good flatness for a 15 GHz (71 GHz to 86 GHz) wideband LNA, a five-stage input/output port transmission line matching method is used. To decrease the package loss and cost, 2nd and 4th SHP mixers were designed. From the measured results, the five-stage LNA shows a gain of 23 dB and a noise figure of 4.5 dB. The 2nd and 4th SHP mixers show conversion losses of 12 dB and 17 dB and input P1dB of -1.5 dBm to 1.5 dBm. Finally, a single-chip receiver based on the 4th SHP mixer shows a gain of 6 dB, a noise figure of 6 dB, and an input P1dB of -21 dBm.

• 한국음향학회지
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• 제25권1호
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• pp.21-29
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• 2006

본 논문에서는 대역분활 광대역 음성부호화기와 이를 위한 고대역 부호화 방법과 구조를 제안한다. 제안하는 광대역 음성부호화기는 광대역 입력 음성신호를 저대역 신호 (OHz-4kHz)와 고대역 신호 (4kHz-8kHz)로 나눈다. 저대역 신호는 G.729 Annex E로 부호화하고, 고대역 신호는 4kbps의 전송률로 제안하는 방법으로 압축된다. 고대역 신호는 LPC 분석 후 신호특성에 따라 모드를 분류된다. stationary 모드에서는 매칭퍼슈잇 알고리즘과 CELP 방법으로 부호화하는 다단계 구조의 혼합 여기신호모델이 적용되며, nonstationary 모드에서는 CELP 방법으로 부호화된다. 제안한 광대역 음성부호화기의 성능을 주관적 방법으로 G.722 48kbps SB-ADPCM, G.722.2 12.85kbps ACELP와 비교를 하였다. 제안한 부호화기는 G.722보다 나은 성능을 보이고, G.722.2보다 나쁘지 않은 성능을 가지는 것을 확인하였다.

• ETRI Journal
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• 제29권5호
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• pp.670-672
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• 2007

An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-${\mu}m$ CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.

• 대한전자공학회논문지SD
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• 제48권12호
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• pp.45-51
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• 2011

본 논문에서는 $0.13{\mu}m$ CMOS 공정을 사용하여 800MHz~5.8GHz 대역 내 다양한 무선통신 표준을 포함하는 광대역 저잡음 증폭기(wideband-LNA)를 구현하였다. 저잡음 특성을 개선하기 위하여 제작한 LNA는 두 단으로 구성되었으며, 입력캐스코드 단 및 잡음신호만을 상쇄시키는 출력 버퍼단으로 구성하였다. 또한, 피드백 저항을 이용함으로써, 광대역 임피던스 매칭 효과 및 넓은 대역폭을 구현하였다. 측정결과, 811MHz~5.8GHz의 주파수 응답과 대역폭 내에서 최대 11.7dB의 전력이득 및 2.58~5.11dB의 잡음지수(NF)를 얻었다. 제작한 칩은 $0.7{\times}0.9mm^2$의 면적을 가지며 1.2V의 전원전압에서 12mW의 낮은 전력을 소모 한다.

• 한국전자파학회논문지
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• 제22권1호
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• pp.76-80
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• 2011

본 논문에서는 3~5 GHz의 동작 주파수를 가지는 0.18-${\mu}m$ CMOS 저전력/광대역 저잡음 증폭기 구조를 제안한다. 제안하는 광대역 저잡음 증폭기는 광대역 입력 정합, 발룬 기능, 그리고 우수한 노이즈 특성을 얻기 위해 노이즈 제거 회로 구조를 채택하였다. 특히, 2차 LC-대역 통과 필터를 증폭기의 부하로 구현함으로써 기존에 발표된 문헌들보다 최소 전력을 소모하면서 높은 전력 이득과 낮은 잡음 지수를 얻을 수 있었다. 본 논문에서 제안하는 저잡음 증폭기는 1.8 V 공급 전압으로부터 단지 3.94 mA의 전류를 소모하며, 모의 실험 결과, 3~5 GHz UWB 대역에서 전력 이득은 최소 +17 dB 이상, 잡음 지수는 최대 +4 dB 이하, 그리고 입력 IP3는 -15.5 dBm을 가진다.