• Transactions on Electrical and Electronic Materials
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• v.1 no.1
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• pp.6-11
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• 2000

The hydrogen plasma treatment of silicon wafers in the reactive ion-etching mode was studied for the application to silicon-on-insulator wafers which were prepared using the wafer bonding technique. The chemical reactions of hydrogen plasma with surface were used for both surface activation and removal of surface contaminants. As a result of exposure of silicon wafers to the plasma, an active oxide layer was found on the surface. This layer was rendered hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposing time and power. In addition, the surface became smoother with the shorter plasma exposing time and power. The value of initial surface energy estimated by the crack propagation method was 506 mJ/㎡, which was up to about three times higher as compared to the case of conventional direct using the wet RCA cleaning method.

• Journal of Power System Engineering
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• v.5 no.4
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• pp.11-17
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• 2001

Micronization of sensor is a trend of the silicon sensor development with regard to a piezoresistive silicon pressure sensor, the size of the pressure sensor diaphragm have become smaller year by year, and a microaccelerometer with a size less than $200{\sim}300{\mu}m$ has been realized, In this paper, we study some of the bonding processes of SCS(single crystal silicon) insulator wafer for the microaccelerometer. and their subsequent processes which might affect thermal loads. The finite element method(FEM) has been a standard numerical modeling technique extensively utilized in micro structural engineering discipline for design of SCS insulator wafers. Successful temperature distribution analysis and design of the SCS insulator wafers based on the tunneling current concept using microaccelerometer depend on the knowledge about normal mechanical properties of the SCS and $SiO_2$ layer and their control through manufacturing processes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.311-317
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• 2008

The measurement of dark ${\sigma}_D$, gamma-induced ${\sigma}_{\gamma}$ conductivities and the expected conductivity modulation ${\Delta}_{\sigma}$ in silicon wafers/samples is studied for developing a new technique for carrier lifetime evaluation. In this paper a simple method is introduced to find the carrier lifetime variations with the measured conductivity and conductivity modulation under dark and gamma irradiation conditions. It will be concluded that this simple method enables us to give an improved wafer evaluation, processing and quality control in the field of photovoltaic materials and other electronic devices.

• Journal of Korean Institute of Industrial Engineers
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• v.34 no.3
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• pp.296-307
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• 2008

A semiconductor production system has sophisticated manufacturing operations and needs high capital investment for its expensive equipment, which warrants efficient real-time flow control for wafers. In the bay, we consider material handling equipment that can handle multiple carriers of wafers. The dispatching logic first determines the transportation time of each carrier to its destination by each unit of transportation equipment and uses this information to determine the destination machine and target carrier. When there is no available buffer space at the machine tool, the logic allows carriers to stay at the buffer of a machine tool and determine the delay time, which is used to determine the destination of carriers in URL. A simulation study shows this dispatching logic performs better than the procedure currently in use to reduce the mean flow time and average WIP of wafers and increase efficiency of material handling equipment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.176-180
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• 2003

Tri-crystalline silicon (Tri-Si) wafers have three different orientations and three grain boundaries. In this paper, tri-Si wafers have been used for the fabrication of buried contact solar cells. The optical and micro-structural properties of these cells after texturing in KOH solution have been investigated and compared with those of cast multi-crystalline silicon (multi-Si) wafers. We employed a cost effective fabrication process and achieved buried contact solar cell (BCSC) energy conversion efficiencies up to 15% whereas the cast multi-Si wafer has efficiency around 14%.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.1
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• pp.85-91
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• 2004

The sapphire wafers for blue light emitting devices were manufactured by the implementation of the surface machining technology based on micro-tribology. This process has been performed by chemical and mechanical polishing process. The sapphire crystalline wafers were characterized by double crystal X-ray diffraction. The sample quality of sapphire crystalline wafer at surfaces has a full width at half maximum of 89 arcsec. The surfaces of sapphire wafer were mechanically affected by residual stress during the polishing process. The wave pattern of optical interference of sapphire wafer implies higher abrasion rate in the edge of the wafer than its center from the Newton's ring.

• Journal of the Korean institute of surface engineering
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• v.24 no.4
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• pp.206-214
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• 1991

In the basic study of selective electroless Ni plating of Si wafers, plating rate and physical properties are investigated to obtain optimum conditions of contact hole filling. Si wafers are excellently activated in the concentration of 0.5M IF, 1mM PdCl2, 2mM EDTA at $70^{\circ}C$, 90sec. The optimum condition of Ni-B deposition on p-type Si wafers is 0.1M NiSO4, 0.11M Citrate, $70^{\circ}C$, pH6.8, 8mM DMAB. The main factor in the sheet resistences variation of films is amorphous and on heat treating matrix was transformed into a stable phase (Ni+Ni3B) at $300-400^{\circ}C$. But pH or DMAB concentration in the plating solution doesn't play role of heat-affected phase change.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.12
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• pp.1072-1080
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• 2013

In a the present day, many vision inspection techniques are used in productive industrial areas. In particular, in the semiconductor industry the vision inspection system for wafers is a very important system. Also, inspection techniques for semiconductor wafer production are required to ensure high precision and fast inspection. In order to achieve these objectives, parallel processing of the inspection algorithm is essentially needed. In this paper, we propose the GPU (Graphical Processing Unit)-based parallel processing algorithm for the fast inspection of semiconductor wafers. The proposed algorithm is implemented on GPU boards made by NVIDIA Company. The defect detection performance of the proposed algorithm implemented on the GPU is the same as if by a single CPU, but the execution time of the proposed method is about 210 times faster than the one with a single CPU.

• Journal of the Semiconductor & Display Technology
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• v.1 no.1
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• pp.9-13
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• 2002

A polyimide-type electrostatic chuck (ESC) was fabricated for the application of holding 8-inch silicon wafers in the oxide etching equipment. For the fabrication of the unipolar ESC, core technologies such as coating of polyimide films and anodizing treatment of aluminum surface were developed. The polyimide films were prepared on top of thin coated copper substrates for the good electrical contacts, and the helium gas cooling technique was used for the temperature uniformity of the silicon wafers. The ESC was essentially working with an unipolar operation, which was easier to fabricate and operate compared to a bipolar operation. The chucking force of the ESC has been measured to be about 580 gf when the applied voltage was 1.5 kV, which was considered to be enough force to hold wafers during the dry etching processing. The employment of the ESC in etcher system could make 8% enhancement of the wafer processing yield.

• Journal of the Semiconductor & Display Technology
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• v.13 no.1
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• pp.13-17
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• 2014

Since the semiconductor manufacturing requires the silicon wafers with extraordinary degree of surface flatness, the surface polishing of wafers from ingot cutting is an important process for deciding surface quality of wafers. The present study introduces the development of wafer polishing equipment and, especially, the wafer polishing head that employs the forced self-driving of installed silicon wafer as well as the wax wafer mounting technique. A series of wafer polishing tests have been carried out to investigate the effects of self-driving function in wafer polishing head. The test results for wafer planarization showed that the LLS counts and SBIR of polished wafer surfaces were generally improved by adopting the self-driven polishing head in wafer polishing stations.