• Korean Journal of Materials Research
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• v.4 no.2
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• pp.127-135
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• 1994

We investigated the bonding interfaces of directly-bonded Si-Si and $Si-Sio_{2}$/Si wafer pairs. By the angle lapping-delineation, anisotropic etching, and (FIR)-TEM observation methods, we studied on the interface defects and the transient region originated from the interface stress, the various types of voids, the formation and stability of interfacial oxide. We also compared the interface image of the bonded $Si-Sio_{2}$ with that of a typically grown $Si-Sio_{2}$.

• Transactions on Electrical and Electronic Materials
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• v.3 no.1
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• pp.4-8
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• 2002

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3279-3281
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• 1999

This paper describes a method of direct wafer bonding using surfaces activated by a radio-frequency hydrogen plasma. The hydrogen plasma cleaning of silicon in the RIE mode was investigated as a pretreatment for silicon direct bonding. The cleaned silicon surface was successfully terminated by hydrogen, The hydrogen-terminated surfaces were rendered hydrophilic, which could be wetted by Dl water rinse. Two wafers of silicon and silicon dioxide were contacted to each other at room temperature and postannealed at $300{\sim}1100^{\circ}C$ in an $N_2$ atmosphere for 2 h. From the AFM results, it was revealed that the surface became rougher with the increased plasma exposure time and power. The effect of the plasma treatment on the surface chemistry was investigated by the AES analysis. It was shown that the carbon contamination at the surface could be reduced below 5 at %. The interfacial energy measured by the crack propagation method was 122 $mJ/m^2$ and 384 $mJ/m^2$ for RCA cleaning and hydrogen plasm, respectively.

• Journal of Sensor Science and Technology
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• v.13 no.4
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• pp.264-269
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• 2004

This paper describes on an advanced technology of 3C-SiC/Si(100) wafer direct bonding using PECVD oxide to intermediate layer for SiCOI(SiC-on-Insulator) structure because it has an attractive characteristics such as a lower thermal stress, deposition temperature, more quick deposition rate and higher bonding strength than common used poly-Si and thermal oxide. The PECVD oxide was characterized by ATR-FTIR. The bonding strength with variation of HF pre treatment condition was measured by tensile strength measurement system. After etch-back using TMAH solution, roughness of 3CSiC surface crystallinity and bonded interface was measured and analyzed by AFM, XRD, and SEM respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.47-51
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• 2000

A modified direct bonding technique employing a wet chemical deposition of $SiO_2$ film on a wafer surface to be bonded is proposed for the fabrication of Si-$SiO_2$-Si structures. Structural and electrical quality of the bonded wafers is studied. Satisfied insulating properties of interfacial $SiO_2$ layers are demonstrated. Elastic strain caused by surface morphology is investigated. The diminution of strain in the grooved structures is semi-quantitatively interpreted by a model considering the virtual defects distributed over the interfacial region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.10
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• pp.779-784
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• 2001

In this work, we studied the characteristics of nitride films for the optimization of PMD(pro-metal dielectric) linear process, which can be applied to the recent semiconductor manufacturing process. We split the deposit condition of nitride films into four parts such as PO(protect overcoat) nitride, baseline, low hydrogen and high stress and low hydrogen, respectively. We tried to find out correlation between BPSG deposition and densification. In order to analyze the changes of Si-H and Si-NH-Si bonding density, we used FTIR area method. We also investigated the crack generation on wafer edge after BPSG densification, and the changes of nitride film stress as a function of RF power variation to judge whether the deposited films.

• Journal of the Korean Vacuum Society
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• v.8 no.4A
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• pp.465-469
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• 1999

In this paper, spacer process for FED (Field Emission Display ) was developed with the glass to glass anodic bonding technology using Al film as an interlayer. Characteristics, current density-time curves and force of the anodic boding were measured on various thickness of Al film; 1000$\AA$, 2000$\AA$, 3000$\AA$, 4000$\AA$ and 500$\AA$. Holders for spacer were fabricated with photosensitive glass and (110) Si wafer by bulk micromachining. Spacers was formed on glass substrate by spacer glass to glass anodic bonding and an evacuated panel was fabricated to prove the potential of application for FED.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.1
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• pp.41-47
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• 1992

In SFB Process, after 110$0^{\circ}C$ annealing in wet OS12T(95$^{\circ}C$ HS12TO bubbling) atmosphere, the existence of the interfacial oxide film in micro-gap at Si-Si bonding interface was identified. The angle lapping/staining and SEM morphologies of bonding interface showed that the growing behavior of interfacial oxide made a contribution to eliminate the micro-gaps having a width of 200-300$\AA$. In case of the diodes composed of p-n wafer pairs made by SFB processes, the annealed one in wet OS12T atmosphere exhibited a dielectric breakdown phenomena of interfacial oxide at 37-40 volts d.c.

• Journal of the Korean Society for Precision Engineering
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• v.26 no.12
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• pp.9-17
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• 2009

• Journal of the Korean Ceramic Society
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• v.35 no.6
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• pp.535-542
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• 1998

SOI(silicon oninsulator) was fabricated through the direct bonding of a hydrophilized single crystal Si wafer and a thermally oxidized SiO2 thin film to investigate the stacking faults in silicon at the Si/SiO2 in-terface. At first the oxidation kinetics of SiO2 thin film and the stacking fault distribution at the oxidation interface were investigated. The stacking faults could be divided into two groups by their size and the small-er ones were incorporated into the larger ones as the oxidation time and temperature increased. The den-sity of the smaller ones based critically lower eventually. The SOI wafers directly bonded at the room temperature were annealed at 120$0^{\circ}C$ for 1 hour. The stacking faults at the bonding and oxidation interface were examined and there were anomalies in the distributions of the stacking faults of the bonded region to arrange in ordered ring-like fashion.