• Journal of Astronomy and Space Sciences
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• v.21 no.4
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• pp.481-492
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• 2004

We report the successful fabrication and I-V curve superconductivity test results of the Nb/Al-based superconducting tunnel junctions. STJs with side-lengths of 20, 40, 60 and $80{\mu}m$ were fabricated by deposition of polycrystalline Nb/Al/AlOx/Al/Nb 5-layer thin films incorporated on a 3-inch Si wafer. STJ was designed by $Tanner^{TM}$ L-Edit 8.3 program, and fabricated in SQUID fabrication facility, KRISS. S-layer STJ thin-films were fabricated using UV photolithography, DC magnetron sputtering, Reactive ion etching, and CVD(Chemical Vapor Deposition) techniques. Superconducting state test for STJ was succeeded in 4K with liquid helium cooling system. Their performance indicators such ie energy gap, normal resistance, normal resistivity, dynamic resistance, dynamic resistivity, and quality factor were measured from I-V curve. Fabricated Nb/Al STJ shows $11\%$ higher FWHM energy resolution than genuine Nb STJ.

• Journal of Powder Materials
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• v.22 no.5
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• pp.321-325
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• 2015

The triboelectric property of a material is important to improve an efficiency of triboelectric generator (TEG) in energy harvesting from an ambient energy. In this study, we have studied the TEG property of a semiconducting $SnO_2$ which has yet to be explored so far. As a counter triboelectric material, PET and glass are used. Vertical contact mode is utilized to evaluate the TEG efficiency. $SnO_2$ thin film is deposited by atomic layer deposition on bare Si wafer for various thicknesses from 5.2 nm to 34.6 nm, where the TEG output is increased from 13.9V to 73.5V. Triboelectric series are determined by comparing the polarity of output voltage of 2 samples among $SnO_2$, PET, and glass. In conclusion, $SnO_2$, as an intrinsic n-type material, has the most strong tendency to be positive side to lose the electron and PET has the most strong tendency to be negative side to get the electron, and glass to be between them. Therefore, the $SnO_2$-PET combination shows the highest TEG efficiency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.603-608
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• 2018

Although the voltage-applied discharge method is most widely used in the semiconductor and display industries, periodic management costs are incurred because the method causes defects due to the absorption of ambient fine dust and causes emitter tip contamination due to the discharge. The emitter tip contamination problem is caused by the accumulation of fine particles in ambient air due to the corona discharge of the ionizer. Fuzzy ball generation accelerates the wear of the emitter tip and deteriorates the performance of the ionizer. Although a mechanical cleaning method using a manual brush or an automatic brush is effective for contaminant removal, it requires management of additional mechanical parts by the user. In some cases, contaminants accumulated in the emitter may be transferred to the wafer or product. In order to solve this problem, we developed an ionizer for a clean environment that can remove the pencil-type emitter tip and directly ionize the surrounding gas molecules using the tungsten wire located inside the ion tank. As a result of testing and certification by the Korea Institute of Machinery and Materials, the average concentration was $0.7572particles/ft^3$, the decay time was less than two seconds, and the ion valance was 7.6 V, which is satisfactory.

• Resources Recycling
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• v.22 no.2
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• pp.22-28
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• 2013

In the present study, the possibility of recovering and recycling the silicon carbide(SiC) from a silicon sludge by removing Fe and Si impurities was investigated. Si and SiC were separated from the silicon sludge using centrifugation. The separated SiC concentrate consisted of Fe, Si and SiC, in which Fe and Si were removed to recover the pure SiC. Leaching with acid/alkali solution was compared with the vapor-phase chlorination. The Fe concentration removed in the SiC was 49 ppm, and it was separated by leaching with 1 M HCl solution at $80^{\circ}C$ for 1 h. The Si concentration removed in the SiC was 860 ppm, and it was separated by leaching with 1M NaOH solution at $50^{\circ}C$ for 1 h. The SiC concentrate was chlorinated in a tubular reactor, 2.4 cm in diameter and 32 cm in length. The boat filled with SiC concentrate was located at the midpoint of the alumina tube, then, the chlorine and nitrogen gas mixture was introduced. The Fe and Si concentration removed in the SiC were 48 ppm and 405 ppm, respectively, at $500^{\circ}C$ reactor temperature, 4 h reaction time, 300 cc/min gas flow rate, and 10% $Cl_2$ gas mole fraction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.80-89
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• 2006

The rapid development of process technology and the introduction of new materials not only make it difficult for process control but also as a result increase process variations. These process variations are barriers to successful implementation of design circuits because there are disparities between data on layout and that on wafer. This paper proposes a new design environment to determine the interconnect worstcase with accuracy and speed so that the interconnect effects due to process-induced variations can be applied to designs of $0.13{\mu}m$ and below. Common Geometry and Maximum Probability methods have been developed and integrated into the new worstcase optimization algorithm. The delay time of the 31-stage Ring Oscillator, manufactured in UMC $0.13{\mu}m$ Logic, was measured, and the results proved the accuracy of the algorithm. When the algorithm was used to optimize worstcase determination, the relative error was less than 1.00%, two times more accurate than the conventional methods. Furthermore, the new worstcase design environment improved optimization speed by 32.01% compared to that of conventional worstcase optimizers. Moreover, the new worstcitse design environment accurately predicted the worstcase of non-normal distribution which conventional methods cannot do well.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.33-38
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• 2001

We investigate the via-size dependance of as-electroplated- and reflow-bump shapes for realizing both high-density and high-aspect ratio of solder bump. The solder bump is fabricated by subsequent processes as follows. After sputtering a TiW/Al electrode on a 5-inch Si-wafer, a thick photoresist for via formation it obtained by multiple-codling method and then vias with various diameters are defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation the under ball metallurgy (UBM) structure with Ti-adhesion and Cu-seed layers is sputtered on a sample. Cu-layer and Sn/pb-layer with a competition ratio of 6 to 4 are electroplated by a selective electroplating method. The reflow-bump diameters at bottom are unchanged, compared with as-electroplated diameters. As-electroplated- and reflow-bump shapes, however, depend significantly on the via size. The heights of as-electroplated and reflow bumps increase with the larger cia, while the aspect ratio of bump decreases. The nearest bumps may be touched by decreasing the bump pitch in order to obtain high-density bump. The touching between the nearest bumps occurs during the overplating procedure rather than the reflowing procedure because the mushroom diameter formed by overplating is larger than the reflow-bump diameter. The arrangement as zig-zag rows can be effective for realizing the flip-chip-interconnect bump with both high-density and high-aspect ratio.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.65-74
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• 2013

The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.

• Korean Chemical Engineering Research
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• v.44 no.5
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• pp.513-519
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• 2006

We developed two kinds of the microchip for application to electrophoresis based on both glass and quartz employing the MEMS fabrications. The poly-Si layer deposited onto the bonding interface apart from channel regions can play a role as the optical slit cutting off the stray light in order to concentrate the UV ray, from which it is possible to improve the signal-to-noise (S/N) ratio of the detection on a chip. In the glass chip, the deposited poly-Si layer had an important function of the etch mask and provided the bonding surface properly enabling the anodic bonding. The glass wafer including more impurities than quartz one results in the higher surface roughness of the channel wall, which affects subsequently on the microflow behavior of the sample solutions. In order to solve this problem, we prepared here the mixed etchant consisting HF and $NH_4F$ solutions, by which the surface roughness was reduced. Both the shape and the dimension of each channel were observed, and the electroosmotic flow velocities were measured as 0.5 mm/s for quartz and 0.36 mm/s for glass channel by implementing the microchip electrophoresis. Applying the optical slit with poly-Si layer provides that the S/N ratio of the peak is increased as ca. 2 times for quartz chip and ca. 3 times for glass chip. The maximum UV absorbance is also enhanced with ca. 1.6 and 1.7 times, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.1
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• pp.114-124
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• 2011

In this paper, we present a 2 GHz compact analog phase shifter with linear phase-tune characteristic. The compact phase shifter was designed base on a lumped all pass network and implemented using a ceramic substrate fabricated with thin-film technique. For a linear phase-tune characteristic, a capacitance of the varactor diode for a tuning voltage was linearized by connecting series capacitor and subsequently produced an almost linear capacitance change. The inductor and bias circuit in the all pass network was implemented using a spiral inductors for small size, which results in the size reduction to $4\;mm{\times}4\;mm$. In order to measure the phase shifter using the probe station, two CPW pads are included at the input and output. The fabricated phase shifter showed an insertion loss of about 4.2~4.7 dB at 2 GHz band and a total $79^{\circ}$ phase change for DC control voltage from 0 to 5 V, and showed linear phase-tune characteristic as expected in the design.