• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.1239-1243
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• 2004

A novel voltage-current reference circuit for stable voltage-current applications is Proposed. Circuits for a positive and for a negative voltage-current reference are presented and are designed with commercial CMOS technology. The voltage-current reference that is stable over ambient temperature variations is an important component of most data acquisition systems. These results are verified by the HSPICE simulation $0.8{\mu}m$ parameter. As the result, the temperature dependency of output voltage and output current each is $0.57mV/^{\circ}C$, $0.11{\mu}A/^{\circ}C$ and the power dissipation is 1.8 mV on 5V supply voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1077-1080
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• 1998

In this paper, a simple low-power current-mode CMOS wotage reference circuit is proposed. The reference circuit of enhancement-mode MOS transistors and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a threshold voltage. The designed circuit has been simulated using a $0.65\mu\textrm{m}$ n-well CMOS process parameters. The simulation results show that the reference circuit has a temperature coefficient less than $7.8ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.079%/V for a temperature range from $-30^{\circ}C$ to $130^{\circ}C$ and a VDD range from 4.0V to 12V. The power consumption is 105㎼ for VDD=5V and $T=30^{\circ}C.$ The proposed reference circuit can be designed to generate a wide range of reference voltages owing to its current-mode operation.

• Journal of information and communication convergence engineering
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• 제7권2호
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• pp.215-218
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• 2009

In this paper, temperature stable current and voltage references using simple CMOS bias circuit are proposed. To obtain temperature stable characteristics of bias circuit a bandgap reference concept is used in a conventional circuit. The parasitic bipolar transistors or MOS transistors having different threshold voltage are required in a bandgap reference. Thereby the chip area increase or the extra CMOS process is required compared to a standard CMOS process. The proposed reference circuit can be integrated on a single chip by a standard CMOS process without the extra CMOS process. From the simulation results, the reference current variation is less than ${\pm}$0.44% over a temperature range from - $20^{\circ}C$ to $80^{\circ}C$. And the voltage variation is from - 0.02% to 0.1%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.89-92
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• 2001

In this paper, a simple low-power CMOS current reference circuit is proposed. The reference circuit includes parasitic pnp BJTs and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a base-to-emitter voltage. The designed circuit has been simulated using a 0.25${\mu}{\textrm}{m}$ n-well CMOS process parameters. The simulation results show that the reference current is 34.96$mutextrm{A}$$\pm$0.04$mutextrm{A}$ in the temperature range of -2$0^{\circ}C$ to 12$0^{\circ}C$ The reference current varies less than 0.6% when the power supply voltage changes from 2.5V to 3.5V For $V_{DD=5V}$ and T=3$0^{\circ}C$ the power consumption is 520㎼ during normal operation but reduces to 0.l㎻ during power-down mode.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.528-533
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• 2016

A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage $V_{reg}$ for the BG core and Op-Amp rather than the VDD. These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a $0.35{\mu}m$ CMOS technology. The BGR circuit occupies $0.024mm^2$ of the die area and consumes $200{\mu}W$ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 dB at frequencies up to 1 kHz and -55 dB at 1 MHz without additional circuits for the curvature compensation. A temperature coefficient of $60 ppm/^{\circ}C$ is obtained in the range of -40 to $120^{\circ}C$.

• 전자공학회논문지A
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• 제33A권4호
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• 전자공학회논문지C
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• 제34C권12호
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• pp.37-42
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• 1997

A new temperature and supply-insensitive CMOS current reference circuit was designed and tested. Te temperature insensuitivity was achieved by eliminating the mobility dependence term through the multiplication of two current components, one which is proportional to mobility and the other which is inversely proportional to mobility, by using a newly designed CMOS square root circuit. The CMOS sqare root circuit was derived from its bipolar counterpart by operating the MOS transistors in the subthreshold region. The supply insensitivity was achieved by using an internal voltage generator. Te test chip was designed ans sent out for fabrication by using a 2.mu.m double-poly double-metal n-well CMOS technology. When an external voltage source was used for the square root circuit, the maximum variation and the average temperature sensitivity were measured to be 3% and 21.4ppm/.deg.C, respectively, for the temperature range of -15~130.deg.C. The maximum current variation with supply voltage was measured to be 3% within the commerical supply voltage range of 4.5~5.5V at 30.deg. C.

• 전자공학회논문지
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• 제52권2호
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• pp.106-111
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• 2015

일반적으로 기준전압 생성기는 쌍안정성을 가지므로 이를 올바른 상태에서 동작시키기 위해서는 적절한 시동회로가 필요하다. 본 논문에서는 저전압 기준전압 발생기를 위한 새로운 시동회로를 제안한다. 제안한 시동회로는 기준전압발생기의 상태를 결정하기 위하여 기준전압 발생기의 BJT에 흐르는 전류를 측정한다. 기준전압발생기가 올바른 상태에 있을 때 이 전류가 가지는 값은 잘 정의되므로 이를 통하여 회로의 상태를 신뢰성 있게 결정할 수 있다. 전류는 내부에 오프셋 전압을 갖는 비교기를 이용하여 측정하였다. 130nm CMOS 공정을 이용하여 설계를 하였으며, 레이아웃에서 추출한 기생 성분을 포함하는 Monte-Carlo 시뮬레이션을 통해 회로의 성능을 검증 하였다. 제안된 시동회로를 사용하는 기준전압발생기에 850mV 이상의 전원 전압이 가해질 경우, 소자에 미스매치가 있더라도 안정적으로 기준전압 생성기가 시동하는 것을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.585-586
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• 2008

In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented. In order to cope with the narrow input common-mode range of the OpAmp in the reference circuit, shunt resistive voltage divider branches were deployed. High gain OpAmp was designed to compensate intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18um CMOS process with nominal Vth of 420mV and -450mV for nMOS and pMOS transistor respectively. The total power consumption including OpAmp is less than 50uW.

• 대한전자공학회논문지SD
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• 제40권4호
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• pp.42-50
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• 2003

본 논문에서는 시스템의 클럭을 안정적으로 공급하는 집적화 한 내장형 RC oscillator의 구현에 관한 논문이다. 기존의 RC oscillator는 온도에 따라 주파수변화가 약 15%정도 변화가 있는데 이는 온도에 따른 저항값의 변화와 schmit trigger의 기준전압이 온도에 따라 변화하기 때문이다. 본 연구에서는 온도에 따른 주파수 변화를 최소화하는 방법으로 CMOS bandgap과 온도에 따른 전류의 변화를 이용하였다. CMOS bandgap으로 기준 전압을 얻고 온도에 따라 증가하는 전류원과 온도에 따라 감소 하는 전류원을 서로 합하면 온도에 따라 일정한 전류를 얻어 주파수의 변화를 약 3%이내로 유지하는 회로를 제안한다.