• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.270-273
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• 2003

The design, fabrication, and measured result of a 4.7 GHz differential VCO (Voltage Controlled Oscillator) for a 5.2 GHz WLAN (Wireless Local Area Network) applications is presented. The circuit is designed in a 0.35 mm technology employing three metal layers. The design is based on a fully integrated LC tank using spiral inductors. Measured tuning range is 10% of oscillation frequency with a control voltage from 0 to 3.0 V. Oscillation power of $\square$ 2.3 dBm at 4.63 GHz is measured with 21 mA DC current at 3V supply. The phase noise is $\square$ 104.17 dBc/Hz at 1 MHz offset.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.295-301
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• 2008

Recently, the demand on mm-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the mm-wave frequency band have been traditionally implemented in III-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled mm-wave circuits realized in a Si CMOS technology. In this work, a 58 GHz CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a $0.13-{\mu}m$ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the mm-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 GHz with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 dBc/Hz at 5 MHz offset was achieved. The output power varied around -20 dBm over the measured tuning range. The circuit drew current (including buffer current) of 10 mA from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 dBc/Hz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1104-1112
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• 2013

This paper presents a wideband Colpitts voltage controlled oscillator(VCO) with nanosecond startup time and a center frequency of 8.35 GHz for a new bubble-type motion detector that has a bubble-layer detection zone at the specific distance from itself. The VCO circuit consists of two parts; one is a negative resistance part with a HEMT device and Colpitts feedback structure and the other is a resonator part with a varactor diode and shorted shunt microstrip line. The shorted shunt microstrip line and series capacitor are utilized to compensate for the input reactance of the packaged HEMT that changes from capacitive values to inductive values at 8.1 GHz due to parasitic package inductance. By tuning the feedback capacitors which determine negative resistance values, this paper also investigates startup time improvement with the negative resistance variation and tuning bandwidth improvement with the reactance slope variation of the negative resistance part. The VCO measurement shows the tuning bandwidth of 2.3 GHz(28 %), the output power of 4.1~7.5 dBm and the startup time of less than 2 nsec.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.273-279
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• 2013

In this paper, a novel split ring resonator is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator, and oscillator for 5.8GHz band is designed using proposed split ring resonator. At the fundamental frequency of 5.8GHz, 7.22dBm output power and -83.5 dBc@100kHz phase noise have been measured for oscillator with split ring resonator. The phase noise characteristics of oscillator is improved about 9.7dB compared to one using the general ${\lambda}$/4 microstrip resonator. Because it is possible that varactor diode or lumped capacitor is placed on the gaps of split ring resonator, resonant frequency can be controlled by bias voltage. We can design voltage controlled oscillator using proposed split ring resonator. Thus, due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1581-1586
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• 2012

In this paper, a novel resonator using ring type DGS is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator, and oscillator for 5.8GHz band is designed using proposed DGS resonator. The ring type DGS resonator is composed of DGS cell etched on ground plane under $50{\Omega}$ microstrip line. At the fundamental frequency of 5.8GHz, 7.6dBm output power and -82.7 dBc@100kHz phase noise have been measured for oscillator with ring type DGS resonator. The phase noise characteristics of oscillator is improved about 9.5dB compared to one using the general ${\lambda}/4$ microstrip resonator. Because it is possible that varactor diode or lumped capacitor is placed on the gaps of ring type DGS, resonant frequency can be controlled by bias voltage. We can design voltage controlled oscillator using proposed ring type DGS resonator. Thus, due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.122-128
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• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.619-624
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• 2002

In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed (sequency divider has designed in a standard 0.25㎛ CMOS technology To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65㎛ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz a tuning range of $\pm$10%, and a gain of 154HHz/V. The simulated frequency synthesizer performance has a settling time of 1.5$\mu$s, a frequency range from 820MHz to IGHz and power consumption of 70mW at 2.5V power supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1112-1115
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• 1990

Described is a new control signal transmission system which utilizes an optical fiber to transmit 2-bit control signals from the transmitter to receiver. In the transmitter the DC series control voltages are converted into the multiple frequency signals by voltage controlled oscillator (VCO). The multiple frequency signals can easily be transmitted by optical fiber. In the receiver the multiple frequency signals can be detected by analog or digital circuits and then be converted into 2-state control signals which can be used for a variety of applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.83-87
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• 2004

Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.