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Design of Frequency Synthesizer using Novel Architecture Programmable frequency Divider  

김태엽 (청주대학교 이공대학 전자공학과)
박수양 (실리콘 웍스)
손상희 (청주대학교 이공대학 정보통시공학부)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.27, no.6C, 2002 , pp. 619-624 More about this Journal
Abstract
In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed (sequency divider has designed in a standard 0.25㎛ CMOS technology To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65㎛ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz a tuning range of $\pm$10%, and a gain of 154HHz/V. The simulated frequency synthesizer performance has a settling time of 1.5$\mu$s, a frequency range from 820MHz to IGHz and power consumption of 70mW at 2.5V power supply voltage.
Keywords
programmable frequency divider; frequency synthesizer; dual-modulus prescaler; voltage controlled oscillator;
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