• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.235-238
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• 2001

단일 단말기로부터 멀티 통신이 가능하게 됨에 따라 광대역 또는 듀얼대역에서 사용되는 RF 소자 개발이 중요시되고 있다. 그러므로 소형, 저 비용의 멀티대역 VCO(Voltage Controlled Oscillator)개발이 요구된다. 본 논문에서 GSM/DCN 대역에서 사용 가능한 듀얼밴드 VCO을 설계하였다. 하나의 발진부, 듀얼 공진부, 완충증폭기, 스위치회로로 구성되었으며, 위상 보정 기법을 이용하여 각 밴드에 대한 발진 조건을 만족시키므로 사용 부품의 수를 줄일 수 있어 저 비용, 소형화, 낮은 위상잡음(phase noise)을 얻을 수 있다. 설계된 듀얼 VCO는 GSM 대역에서 -110dBc/Hz(100kHz offset) 이하의 위상 잡음과 DCN 대역에서 -108dBc/Hz(100kHz offset)의 위상 특성을 보인다. 출력전력은 0$\pm$3dBm이며 소비전력 7mA로 만족할만한 성능을 보인다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.470-475
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• 2015

This paper presents a wideband Current-Reused Voltage Controlled Oscillator (VCO) with 2-Step Automatic Amplitude Calibration (AAC). Tuning range of the proposed VCO is from 1.95 GHz to 3.15 GHz. The mismatch of differential voltage is within 0.6 %. At 2.423 GHz, the phase noise is -116.3 dBc/Hz at the 1 MHz offset frequency with the current consumption of 2.6 mA. The VCO is implemented $0.13{\mu}m$ CMOS technology. The layout size is $720{\times}580{\mu}m^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.291-294
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• 2003

The circuit substrate was made from the Low Temperature Cofired Ceramics(LTCC) that a $\varepsilon_\gamma$ was 7.8. Accumulated Varactor and the low noise transistor which were a Surface Mount Device-type element on LTCC substrate. Let passive element composed R, L, C with strip-line of three dimension in the multilayer substrate circuit inside, and one structure accumulate band-pass filter, resonator, a bias line, a matching circuit, and made it. Used Screen-Print process, and made Strip-line resonator. A design produced and multilayer-type VCO(Voltage Controlled Oscillator), and recognized a characteristic with the Spectrum Analyzer which was measurement equipment. Measured multilayer structure VCO is oscillation frequency 1292[MHz], oscillation output -28.38[dBm], hamonics characteristic -45[dBc] in control voltage 1.5[V], A phase noise is -68.22[dBc/Hz] in 100 KHz offset frequency. The oscillation frequency variable characteristic showed 30[MHz/V] characteristic, and consumption electric current is approximately 10[mA].

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1233-1236
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• 2003

This paper proposes a phase-locked loop (PLL) that achieves one-cycle lock acquisition by employing the lock-acquisition circuit (LAC). The LAC produces the initial analog voltage ( v$_{c}$ ) that corresponds to the input frequency. When the transfer curve of the LAC matches that of the voltage-controlled oscillator (VCO), one-cycle locking can be possible. By HSPICE simulations, the proposed LAC is proved to be applicable to any kinds of PLL [1][2][3].].

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.9
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• pp.30-37
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• 2000

In this paper, design and fabrication of miniature voltage-controlled oscillator(VCO) is discussed . Based on the two-port circuit analysis technique, VCO for 900MHz cellular mobile phone is designed and circuit parameters are optimized using the circuit simulator. Using the optimized design parameters, miniature VCO with 6${\times}$6${\times}$1.8 mm$^3$(0.065cc) dimensions is fabricated and experimented. Experimental results show that implemented VCO has -3.5 dBm output power level and 45MHz tunung range, respectively, and has -101.5dB/Hz Phase noise performance at 10 KHz frequency offset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1176-1183
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• 2003

In this paper, miniature voltage-controlled oscillator(VCO) for 1.6 ㎓ PCS band is designed and implemented using the LTCC technique. Circuit level design using commercial components is performed, and passive L, C elements embedded in LTCC substrate is optimized by simulation tools. Embedded passive components are modeled into equivalent circuits and their circuit parameters are extracted for circuit simulation. Utilizing the designed embedded passive elements and 21 layers LTCC substrate, VCO with 4.0${\times}$4.0${\times}$1.6 ㎣ dimensions is designed and fabricated. Developed VCO operates in 2.7 V with 8.5 ㎃ current consumption. The phase noise performance of VCO is below -112.61 ㏈c/㎐ at 100 ㎑ offset and harmonic suppression characteristics is measured above -30 ㏈.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.60-68
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• 2007

A technique is presented to extract differential second harmonic output from common source nodes of a cross-coupled P-& N-FET oscillator. Provided the impedances at the common source nodes are optimized and the fundamental swing at the VCO core stays in a proper mode, it is found that the amplitude and phase errors can be kept within $0{\sim}1.6dB$ and $+2.2^{\circ}{\sim}-5.6^{\circ}$, respectively, over all process/temperature/voltage corners. Moreover, an impedance-tuning circuit is proposed to compensate any unexpectedly high errors on the differential signal output. A Prototype 5-GHz VCO with a 2.5-Hz LC resonator is implemented in $0.18-{\mu}m$ CMOS. The error signal between the differential outputs has been measured to be as low as -70 dBm with the aid of the tuning circuit. It implies the push-push outputs are satisfactorily differential with the amplitude and phase errors well less than 0.34 dB and $1^{\circ}$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.6
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• pp.539-545
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• 2016

In this paper, a novel coupled C type resonator is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator. Oscillator using proposed shorted coupled C type resonator is designed, it has improved phase noise characteristics. At the fundamental frequency of 9.8GHz, 4.87dBm output power and -84.7 dBc@100kHz phase noise have been measured for oscillator with shorted coupled C type resonator. Next, we designed voltage controlled oscillator using proposed shorted coupled C type resonator with varactor diode. The VCO has 33.8MHz tuning range from 9.7807GHz to 9.8145GHz, and phase noise characteristic is -115~-112.5dBc/Hz@100KHz. Due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.