• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 A
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• pp.335-337
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• 2003

The protection against transient instability and consequent out-of-step condition is a major concern for the utility. The unstable system may cause serious damage to system elements such as generators and transmission lines. Therefore, out-of-step detection is essential to operate a system safely. This paper presents the Out-of-Step detection algorithm using voltage frequency variation. The digital filters based on Discrete Fourier Transforms (DFT) to calculate the frequency of a sinusoid voltage are used, and the generator angle is estimated using the variation of the calculated voltage frequency. The proposed out-of-step algorithm is based on the assessment of a transient stability using equal area criterion. The proposed out-of-step algorithm is verified and tested by using EMTP MODELS.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.118-129
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• 2010

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.186-187
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• 2007

In this work, a temperature stable PWM(Pulse width modulation) circuit is proposed. The designed PWM circuit has a temperature dependent current source and a temperature independent voltage to compensate electrical characteristics with operating temperature. The variation of driving current is from about 4% to -6% in the temperature range $0^{\circ}C\;to\;70^{\circ}C$ compared to the current at the room temperature. The variation of bandgap voltage reference is from about 1.3% to -0.2% with temperature when the supply voltage is 3.3 volts. From simulation results, the variation of output pulse width is less than from 0.86% to -0.38% in the temperature range $0^{\circ}C\;to\;70^{\circ}C$.

• 태양에너지
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• 제19권4호
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• pp.63-69
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• 1999

The conventional grid connected PV(Photovoltaic) system has a unstable output pattern due to its dependence on the weather condition, although solar-cell array averagely has a regular output characteristics to have a peak output nearly at noon. Therefore assuming the high density grid connection in the future, this unstable output pattern can be one of the main reasons to generate power disturbance such as voltage variation, frequency variation and harmonic voltage generation in low voltage distribution line. However general grid connected solar-cell system do not have functions to cope with these disturbances. Therefore this study proposed a advanced type grid connected PV system with functions to suppress output power fluctuation due to solar-cell array output variation and showed the levelling effect of fluctuation due to instantaneous array output variation.

• Journal of Electrical Engineering and Technology
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• 제9권4호
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• pp.1210-1216
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• 2014

This paper deals with an application of Teager Energy Operator (TEO) and Energy Separation Algorithm(ESA) to detect and determine various voltage waveform distortions like harmonics, inter-harmonics and frequency variation. Because the TEO and DESA algorithm was initially proposed for speech or communication analysis, its applications are limited to some types of waveform in the power quality analysis area. For example, an undistorted voltage signal is similar with a pure sinusoid. A voltage fluctuation is very similar with an amplitude-modulated signal, from the viewpoint of signal theory. And a continuous frequency variation is similar with a frequency-modulated signal, which is also known as a chirp signal. This paper is written to show that the TEO and DESA algorithm can be used for detecting occurrences of the representative waveform distortions and determining their instantaneous information of amplitude and frequency.

• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1124-1136
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• 2017

Direct Power Control technique has become popular in the grid connected Voltage Source Converter (VSC) applications due to its simplicity, direct voltage vector selection and improved dynamic performance. In this paper, a direct method to determine the effect of voltage vector on the instantaneous active and reactive power variations is developed. An alternative Look Up Table is proposed which minimizes the commutations in the converter and results in minimum reactive power variation. The application of suggested table is established for Shunt Active Power Filter (SAPF) application. The Predictive Direct Power Control method, which minimizes apparent power variation, is further investigated to reduce commutations in converters. Both the methods are validated using 2 kVA laboratory prototype of Shunt Active Power Filters (SAPF).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.375-378
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• 2000

This paper investigated that resonant frequencies of microstrip patch antenna were tunable when piezoelectric materials were used as the antenna substrates. The resonant frequencies of the microstrip antenna using the piezoelectric substrate, like PZT, LiNbO$_3$ were able to be controlled by applied DC voltage. The frequency variation of the air gap antenna was 29MHz when the voltage variation was 14[kV/cm], and the frequency variation of microstrip patch antenna made of LiNbO$_3$substrate was 29MHz when voltage variation was 6[kV/cm].

• 전력전자학회논문지
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• 제18권4호
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• pp.322-332
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• 2013

Conventional single-phase series quasi Z-source voltage compensator can not compensate for voltage sag less than 50% that frequently occurs in the industrial field. In this study, single-phase series quasi Z-source voltage sag-swell compensator which can compensate the voltage variation of entire range is proposed. The proposed system is composed of two quasi Z-source AC-AC converters connected in series with output terminal stage. Voltage sag less than 50% could be compensated by the intersection switching control of the upper converter duty ratio and of the upper converter duty ratio. Also the compensation voltage and its flowchart for each compensation mode are presented for entire sag-swell region. To confirm the validity of the proposed system, a DSP(DSP28335) controlled experimental system was manufactured. As a result, the proposed system could compensate for the voltage sag/swell of 20% and 60%. Finally, voltage compensation factor and THD(Total Harmonic Distortion) according to voltage variation and load change were measured, and voltage quality shows a good results.

• 조명전기설비학회논문지
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• 제27권4호
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• pp.8-15
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• 2013

This paper proposes a DC-link voltage variation compensation method for a 3-level single phase converter for high-speed trains. Since 3-level NPC(Neutral Point Clamped) type converters have the split DC-link causing the inherent problem of voltage fluctuations in the upper and lower capacitors, reducing the voltage difference between the top and bottom capacitors is required. In this paper, compensation time proportional to the voltage difference is added to PWM switching time to solve the voltage variation. The compensation time is obtained by a PI controller. Simulation results demonstrate the validity of the proposed method.

• Journal of Information Processing Systems
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• 제7권1호
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• pp.93-102
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• 2011

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.