• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.10
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• pp.71-79
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• 2008

This paper analyzed the voltage induction phenomena on the telecommunication lines by electromagnetic coupling from high-speed A.C. electrified railway. The induced common mode voltages and the induced differential mode voltage on the telecommunication line was measured by notified standard method in the regulation of Korea. The test lines consist of 2 separated lines of 20 m and 300 m in influence distance each for comparison, with 2km inducing length. The analysis is made on the induced voltages from the different influence distances and the different earthing points, and also on the waveform and spectrum distributions. It is proved that the induction is arisen so good and the measured values are fair enough against noise such as the earth voltage differencing, and the current measuring scheme is also rightful.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.489-494
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• 2001

In this thesis, the microstructure and electrical properties of ZnO varistors were investigated according to ZnO varistors with various formulation. A∼E's ZnO varistor ceramics were exhibited good density, 95% of theory density and low porosity, 5%, wholly. The average grain size of A-E's ZnO varistor ceramics exhibited 11.89$\mu\textrm{m}$, 13.57$\mu\textrm{m}$, 15.44$\mu\textrm{m}$, 11.92$\mu\textrm{m}$, 12.47$\mu\textrm{m}$, respectively. Grain size of C's ZnO varistor is larger and grain size of A and D's are smaller than other varistors. In the microstructure, A∼E's ZnO varistor ceramics sintered at l130$^{\circ}C$ was consisted of ZnO grain(ZnO), spinel phase(Zn$\sub$2.33/Sb$\sub$0.67/O$_4$), Bi-rich Phase(Bi$_2$O$_3$) and inergranular phase, wholly. Reference voltage of A∼E's ZnO varistor sintered at 1130$^{\circ}C$ decreased in order D, E > A > B > C's ZnO varistors. Nonlinear exponent of varistors exhibited high characteristics, above 30, wholly. Consequently, C's ZnO varistor exhibited good nonlinear exponent, 68. Lightning impulse residual voltage of A, B, C and E's ZnO varistors suited standard characteristics, below 12kV at current of 5kA.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.4
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• pp.210-220
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• 2002

We analysised the effect of harmonics on electric machines of substation power system barred on quantitatively measured harmonics and proposed the methods for prevention of harmonics through checking on transformer, rectifier and cable's capacities against harmonics with reference to KEPCO's electricity service standard. In order to analysis harmoninics of silicon rectifier that is power source in DC substation, computer simulations for a substation with TR of high voltage distribution switchboard are performed. Simulation results show that the total harmonic distortion factor becomes smaller for TR primary and receiving points in order rather than silicon rectifier which is harmonic generation source so that the harmonics generated frets each rectifier are outflowed to power supply and high voltage distribution switchboard The result of higher distortion factors of voltage and current for rectifier with 100% load than those with 50 % and 30% indicates that the waveform of voltage and current for the real substation power system at the office-going and the closing hours with heavy loads might be more distorted. As proposed methods for harmonic reduction, the conventional 6 pulse-type for substation is required to be replaced by 12 pulse-type for reduction of 5th and 7th harmonics. The active filter rather than the passive filter is more effective due to severe variance of rectifier loads, but the high cost is price to be paid. In view of installation area and costs, the use of 12 pulse-type transformer is desirable and then the parallel transformer and the rectifier within the substation must be replaced at the same time. Other substations with parallel feeder can use 6 pulse-type transformer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.10-14
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• 2009

We propose a trapezoidal gate AlGaN/GaN high electron mobility transistor(HEMT) to improve the breakdown voltage characteristics and its feasibility is investigated by two-dimensional device simulations. The use of a trapezoidal gate structure appears to be quite effective in dispersing the electric fields concentrated near the gate edge on the drain side from the simulation result. We find that a peak value of the electric field along the 2-DEG channel is reduced by 30%, from 4.8 to 3.5 MV/cm and thereby, the breakdown voltage(Vbr) of the proposed AlGaN/GaN HEMT is increased by about 40%, from 49 to 69 V, compared to those of the standard AlGaN/GaN HEMT.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.55-60
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• 2014

For an high speed communication, a 40GHz VCO was implemented using a 0.11um standard CMOS technology. The mm-wave VCO was designed by a LC type using a spiral inductor, and a simplified architecture with buffers and a smart biasing technique were used to get a high performance. The frequency range of the proposed VCO is 34~40GHz which is suitable for mm-Wave communication system. It has an output power of -16dBm and 16% tuning range. And the phase noise is -100.33dBc/Hz at 1MHz offset at 38GHz fundamental frequency. The total power consumption of VCO including PADs is 16.8mW with 1.2V supply voltage. The VCO achieves the FOMT of -183.8dBc/Hz which is better than previous VOCs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.570-575
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• 2005

Malfunction by electrical surges is a serious problem on earth leakage current breakers(ELBs) used in a low voltage AC power system. In this paper, we tested ELBs according to IEC 61009-1 and KS C 4613 to analyze surge influence on ELB's malfunction. The test by application of surge voltage is specified both standards, but the test by application of surge current is specified only in IEC 61009-1. The experimental results showed that the ELBs used in this test are robust to surge voltage application, but the malfunction occurred to surge current application. Surge current is more frequent than surge voltage in actual situation. Therefore, ELBs should be tested by the surge current, and the domestic standard, KS C 4613, should includes a test procedure by the surge current application.

• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.203-208
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• 2007

This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.3
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• pp.93-100
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• 2002

In this paper, in ordor to examine the relevant technical facts which are very instructive to revise the domestic standard for lightning protection systems, standards and technical guideline for the protection of structure against lightning were reviewed, and several issues of the domestic standards were experimentally investigated. As a consequence, the insulator of relatively low implse voltage and a large percentage of lighting rods is flashovered by relatively low impulse voltage and a lage percentage of lighting current flows through supporting mast. Thus the potential gradient in the vicinity of supporter for lighting rods is extremely increased and the role of lighting propection systems is nullified. It seems obvious that the flashover of insular supporting lighting rod can range from erratic operation of microelectronic devices to minor physical ham or even death, or costly damage electrical equipment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.145-150
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• 2013

This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.