• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.199-202
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• 2002

In general, the background light produced during the reset period deteriorates the dark room contrast ratio in AC PDP. In this paper, we propose a modified ramp reset pulse that can reduce the background light to imperceptible level. In the new reset waveform, the discharges between the scan and sustain electrodes are minimized by applying a positive bias voltage to the sustain electrode and only the weak discharges between the scan and address electrodes occur during the reset period. We adopted a MgO coated phosphor layer to get the same level of voltage margin in the new reset pulse scheme compared to that of the conventional ramp reset pulse one. As a result, the voltage margin is maintained at the same level and the dark room contrast ratio is improved dramatically.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1555-1557
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• 2002

We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

• Journal of Information Display
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• 제2권4호
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• pp.52-56
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• 2001

This paper presents the effects of the phosphor layer morphology related to the discharge volume on the discharge and radiation characteristics of the Red, Green, and Blue cells in an AC-PDP. As the thickness of the phosphor layer increases and the corresponding discharge volume in the cells decreases, the voltage margin decreases due to an increase in the sustain voltage. In contrast, the IR(Infrared) emission, discharge current, and luminance characteristics remain almost unchanged, regardless of any changes in the phosphor layer morphology.

• Journal of Electrical Engineering and Technology
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• 제8권4호
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• pp.719-728
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• 2013

Probabilistic assessment of voltage stability margin (VSM) with existence of correlated wind speeds is investigated. Nataf transformation is adopted to establish wind speed correlation (WSC) model. Based on the saddle-node bifurcation transversality condition equations and Monte Carlo simulation technique, probability distribution of VSM is determined. With correlation coefficients range low to high value, the effect of WSC on VSM is studied. In addition, two risk indexes are proposed and the possible threat caused by WSC is evaluated from the viewpoint of risk analysis. Experimental results show that the presence of correlated wind speeds is harmful to safe and stable operation of a power system as far as voltage stability is concerned. The achievement of this paper gives a detailed elaboration about the influence of WSC on voltage stability and provides a potentially effective analytical tool for modern power system with large-scale wind power sources integration.

• 대한전자공학회논문지SD
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• 제44권1호
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• pp.28-35
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• 2007

SRAM의 전체적인 성능은 공급 전원전압에 크게 영향을 받는다. 본 논문에서는 1-V 이하의 저전압 동작시 주요 이슈가 되는 SRAM 셀의 SNM(Static Noise Margin)과 셀 전류의 크기를 개선하기 위하여 이중 승압 셀 바이어스 기법을 이용한 SRAM 설계기법에 대해 기술하였다. 제안한 설계기법은 읽기 및 쓰기동작시 선택된 SRAM 셀의 워드라인과 load PMOS 트랜지스터의 소스에 연결된 셀 공급전원을 서로 다른 레벨로 동시에 승압함으로써 SRAM 셀의 SNM과 셀 전류를 증가시킨다. 이는 셀 면적의 증가 없이 충분한 SNM을 확보할 수 있으며, 아울러 증가된 셀 전류에 의해 동작속도가 개선되는 장점이 있다. $0.18-{\mu}m$ CMOS 공정을 적용한 0.8-V, 32K-byte SRAM macro 설계를 통해 제안한 설계기법을 검증하였고, 시뮬레이션 결과 0.8-V 공급전원에서 종래의 셀 바이어스 기법 대비 135 %의 SNM 향상과 아울러 동작속도는 31 % 개선되었으며, 이로인한 32K-byte SRAM은 23 ns의 access time, $125\;{\mu}W/Hz$의 전력소모 특성을 보였다.

• 한국안전학회지
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• 제27권4호
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• pp.13-19
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• 2012

The purpose of this study is to extract the major factors related to the deterioration mechanism of white organic light-emitting diodes(WOLED) by performing accelerated testing of temperature, voltage, time, etc., and to develop an accelerated life test(ALT) model. The measurement results of the brightness of the WOLED exhibited that their average brightness tended to increase as the operating voltage increased and that the half-life period of the brightness appeared after approximately 400 hours when the operating voltage was 20V and the ambient temperature was $85^{\circ}C$. It could be seen that although the WOLED showed comparatively the same brightness when the initial acceleration began after the operating voltage was applied to it, its brightness changed excessively after the WOLED's thermal storage had been made. In addition, it was observed that the half-life period was reduced as the ambient temperature and applied voltage increased. The strength of the WOLED which had been maintained in the range of visible light at the maximum load was reduced by the deterioration of the organic light emitting material due to the influence of the operating voltage and temperature, and the reduction of emitted light was small at low voltage and temperature. It could be seen that the failure of the WOLED during the ALT was caused by wear due to load accumulation over time, and that Weibull distribution was appropriate for the life distribution and acceleration was established between test conditions. From the WOLED analysis, it is thought that factors influencing the brightness deterioration are voltage, temperature, etc., and that comprehensive analysis considering discharge control, dielectric tangent margin, etc., would further increase the reliability.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권10호
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• pp.510-514
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• 2004

In this paper, we analytically examine the voltage transfer function dependent on input conditions for an N-Input NAND Gate. The logic threshold voltage, defined as a voltage at which the input and the output voltage become equal, changes as the input condition changes for a static NAND Gate. The logic threshold voltage has the highest value when all the N-inputs undergo transitions and it has the lowest value when only the last input connected to the last NMOS to ground, makes a transition. This logic threshold voltage difference increases as the number of inputs increases. Therefore, in order to provide a near symmetric voltage transfer function, a multistage N-Input Gate consisting of 2-Input Logic Gates is desirable over a conventional N-Input Gate.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.26-30
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• 1999

The constraint condition is the stator voltage and the stator current to operate the motor in the flux weakening region. The maximum current is limited by the inverter current rating and the machine thermal rating. Given DC link voltage to control the motor in the flux weakening the maximum voltage is determined by considering PWM strategy, dead time, voltage drop of the inverter switching device, and the margin of the voltage for current forcing. In this paper, the new method to determine the available maximum voltage is derived by the analythic method and by considering the factors of the voltage drop. So Determining the maximum voltage is very useful to enlarge the speed operation region in the flux weakening operation, the utility of the maximum voltage is increased.

• Transactions on Electrical and Electronic Materials
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• 제16권6호
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• pp.293-302
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• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• 조명전기설비학회논문지
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• 제21권9호
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• pp.7-11
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• 2007

The objective of this study is to evaluate the characteristics of a newly proposed high-speed drive method for the gray scale display for high-resolution plasma display panels(PDP). In the experiment it was found that the characteristics of gray scale display are not closely affected by a priming period below 50[${\mu}s$], the width of the priming period, and that it can be driven stably from the brightest sub-field to the darkest sub-field even though a priming discharge is applied to the 1 TV-field only once. Moreover, from the experimental result, the gray scale pattern of 8-bit and 9 sub-fields was stably displayed in the experimental PDP with scan pulses having the pulse width of 0.7[${\mu}s$]. An address voltage margin of about 25[V] and a sustain voltage margin of about 10[V] was obtained.