• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
• /
• pp.164-170
• /
• 2004

Misfiring is often observed during the high temperature quality assurance test of plasma display panel. This limits the productivity of PDP industry. In this paper, experimental observations on the misfiring at high panel temperature have been performed through time dependent discharge light output and static margin measurement. For the high temperature condition, firing voltage increment is found in both surface and facing discharges. This in turn increases time lag in address discharge, and results in increment of misfiring probability. In order to reduce this kind of misfiring, a new method that applies automatically different slope of ramp erasing pulse on the common electrode according to temperature variation is proposed. The experimental results show that controlling the slope of ramp erasing pulse is quite effective for compensating temperature-dependent variation of reset and address discharge.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1991년도 하계학술대회 논문집
• /
• pp.720-725
• /
• 1991

In this thesis, the lead-lag compensator is designed to improve output characteristics of flyback zero voltage switching quasi-resonant converters. The switch and the diode are assumed ideally. And the SMPS is modelled by state equations with four operation modes. And the model for controller design is also achived by using a state space averaging method, which is continuous time average of state variables every period. The lag, the lead and the lead-lag compensator is designed the SMPS respectively. The time domain analysis and the frequency domain analysis are done for each compensated circuit. It is possible increasing the phase margin and improving the transient response by the compensators. The phase lag compensator has small overshoot comparatively. But the bandwidth is narrower than the others, so it has longest settling time. For the phase lead compensator, the response come to steady-state within short period. But the overshoot is the largest due to its large peak gain. Finally, the phase lead-lag compensator has medium characteristics in the overshoot and the settling time.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1998년도 하계학술대회 논문집 E
• /
• pp.1788-1790
• /
• 1998

The dielectric layers in AC plasma display panel(AC PDP) are essential to the discharge cell structure, because they protect metal electrodes from sputtering by positive ion bombarding in discharge plasma and form a sheath of wall charges which are essential to memory function of AC PDP. This layer should have high dielectric strength and also be transparent because the luminance of PDP is strongly correlated this layer. In this paper, we discussed the dielectric strength and transparency of the dielectric layer under various conditions. As a result, on the $15{\mu}m$ thickness, the minimum dielectric strength was $29V/{\mu}m$ and the transmittance coefficient was about 80% after $570^{\circ}C$ firing process. It can be proposed that the resonable dielectric thickness in AC PDP is $15{\mu}m$ because it has about 80V margin on the maximum applied voltage.

• 조명전기설비학회논문지
• /
• 제18권4호
• /
• pp.22-27
• /
• 2004

새로 제안된 기체방전 AND gate를 3전극 면방전 AC PDP에 적용하기 위하여 DC-AC floating 방전을 사용한 어드레스 방전 특성을 해석하였다. 실험결과 Y 전극을 floating 전극으로 한 floating 방전을 이용하여 어드레스 방전을 개시시킬 수 있었으며 표시방전을 유지시킬 수 있었다. 또한 floating 방전과 타이밍을 일치시켜 보조전극에 DC 프라이밍 방전을 일으켜 줌으로써 floating 방전 공간에 공간전하를 충분히 공급해 주어 그 결과 데이터 전압을 100(V)까지 낮출 수 있었다. 이 DC-AC floating 방전을 사용한 구동방식은 100(V)의 어드레스 동작마진을 얻을 수 있었다.

• 조명전기설비학회논문지
• /
• 제18권5호
• /
• pp.42-47
• /
• 2004

본 연구는 기존에 제안한 방전 AND gate PDP의 문제점을 개선한 연구결과로서 AND gate를 구성하는 DC 방전의 극성을 반대로 설계하여 인접 주사전극에 대한 cross talk 문제를 개선하였다. 또한 기존의 AND gate의 동작이 공간전하에 의한 방전의 비선형성에 의존한 것과는 달리 본 연구에서 제안한 AND gate는 방전 회로에 따라 인가전압이 변화하는 것을 이용한 NOT 논리를 AND gate에 부가하여 동작이 한층 안정해 졌다. 실험 결과4개의 수평 주사전극에 대해 선택적인 어드레스 방전이 가능하였으며 각각 34V와 70V의 AND 방전 및 Data 방전의 동작마진을 얻을 수가 있었다.

• 조명전기설비학회논문지
• /
• 제17권6호
• /
• pp.83-88
• /
• 2003

본 논문에서는 IPM의 전기적인 기생 성분 중에서 성능에 가장 크게 영향을 미치는 밀러 커패시턴스에 의하여 발생하는 오동작을 시뮬레이션을 통하여 증명하고 이를 최소화하기 위한 방법을 제시한다. 게이트와 컬렉트 단자간에 형성되는 밀러 커패시턴스와 밀접하게 관련된 게이트-에미터 사이의 기생 커패시턴스와 게이트 저항과의 상관 관계를 PSpice 시뮬레이션을 통하여 분석한다. 또한 시뮬레이션 결과를 바탕으로 IPM의 오동작을 최소화하기 위한 보조 회로를 삽입한 주문형 IPM을 제시한다. 표준형 IPM과 오동작 방지를 위해 보조회로가 삽입된 주문형 IPM의 실험 파형을 통해서 주문형 IPM이 약 3 [V]의 오동작에 대한 여유 전압을 가짐을 확인할 수 있다.

• 한국조명전기설비학회:학술대회논문집
• /
• 한국조명전기설비학회 2009년도 추계학술대회 논문집
• /
• pp.153-157
• /
• 2009

A Highly efficient Mercury-free Flat Fluorescent Lamp (MFFL) with dielectric barrier Xe gas discharge was developed for an alternative of conventional line-type Cold Cathode Fluorescent Lamps (CCFLs) which shows a wide voltage margin and a stable discharge operation for diffuse glow discharge with an application of a auxiliary electrode. Electro-optic characteristics of the MFFL were examined through the changes in ambient temperature, total pressure and Xe partial pressure. the single cell is expanded into a multi-structured configuration to realize a large sized lamp by a simple repetition of the single cells, and a new driving scheme is proposed for an adaptive brightness control using dual auxiliary electrodes and bi-polar drive scheme. In addition, interesting application of this ultra high luminance flat lamp by the optimization of the gas condition and the pattern of the rear phosphor layer is suggested as a good alternative of daylight lamp source

• 한국조명전기설비학회:학술대회논문집
• /
• 한국조명전기설비학회 2001년도 학술대회논문집
• /
• pp.65-72
• /
• 2001

Power system stabilizer act efficiently to damp the electromechanical oscillations in interconnected power systems. This paper presents an algorithm for the optimal parameter selection of a power system stabilizer in two-area power systems with a series HVDC link. This method is one of the classical techniques by allocating properly pole-zero positions to fit as closely as desired the ideal phase lead between the voltage reference and the generator electrical power and by changing the gain to produce a necessary damping torque over the matched frequency range. Control of HVDC converter and inverter are used a constant current loop. Proper parameters of PI controllers are obtain based on the Root-locus technique in other to have sufficient speed and stability margin to cope with charging reference values and disturbance. The small signal stability arid transient stability studies using the PSS parameters obtained from this method show that a natural oscillation frequency of the studycase system is adequately damped. Also the simulation results using the HVDC converter and inverter parameters obtained from this proposed method show proper current control characteristics. The simulation used in the paper was performed by the Power System Toolbox software program based on MATLAB.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권1호
• /
• pp.20-27
• /
• 2007

An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the two cases of 10pF and 100pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.

• 전기전자학회논문지
• /
• 제18권1호
• /
• pp.37-44
• /
• 2014

In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier's Bandwidth is 50.8MHz and its phase margin is $59.2^{\circ}C$. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from $-40^{\circ}C$ to $125^{\circ}C$ we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a $1{\mu}F$ output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in $0.35{\mu}m$ CMOS process.