• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.712-717
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• 2014

The performance of npn SiGe HBT on thin film SOI is investigated at 32 nm technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 nm FDSOI technology having 10 nm film thickness and 30 nm BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V $V_{CE}$ has very high $f_tBV_{CEO}$ product (839 GHzV). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 dB) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 nm SOI CMOS (usually voltage gain is in the range of 10-20 dB).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.722-725
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• 2004

Voltage step-down characteristics in Ring/Dot type piezoelectric transformer were examined as a function of the area of input electrode when the area of output electrode is fixed. The effects of driving frequency and load resistance on the voltage step-down characteristics were also examined. Voltage gain was greatly dependent on the driving frequency and load resistance, and showed a maximum gain at resonance frequency of the step-down transformer. The frequency where the maximum output voltage appears increased about 0.2% as the load resistance increased from 10 to $150\Omega$. As the area of input electrode increased, the voltage gain and the efficiency of the transformer increased. Frequency dependence of efficiency of the step-down transformer revealed a similar tendency with the voltage gain curves. The maximum efficiency remarked 94% when the input voltage and the load resistance were 20 $V_{PP}$ and $120\Omega$, respectively.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.240-243
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• 2001

This paper presents the digital controller using variable gain for single-phase power factor correction (PFC) converter. Generally, the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This is why input current is distorted under low input voltage. In particular, a digital controller has more time delay than an analog controller which degrades characteristics of control loop. So, it causes the problem that the gain of current control loop isn't increased enough. In addition, the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult. In this paper, the improved digital control method for single-phase power factor converter is presented. The variable gain according to input voltage and input current help to improve current shape. The 800W converter is manufactured to verify the proposed control method.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.545-548
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• 2006

This paper presents control method of a Z-source inverter and their relationships of voltage boost versus modulation index. A maximum boost control is presented to produce the maximum voltage boost(or voltage gain)under a given modulation index. The control method, relationships of voltage gain versus modulation index, and voltage stress versus voltage gain are analyzed in detail and verified by experiment.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.11
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• pp.885-891
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• 2001

Ring/dot-type step-down piezoelectric transformer was manufactured by using Pb[(Mn$\sub$1/3/Sb$\sub$2/3)$\sub$0.05/Zr$\sub$0.475/Ti$\sub$0.475/]O$_3$ ceramics, which have excellent high-power piezoelectric properties. The characteristics of step-down piezoelectric transformer as a function of load resistance at output terminal was examined. Voltage gain was greatly dependent on drive frequency and load resistance, and showed maximum voltage gain at the resonance frequency. The output voltage was linearly increased as the input voltage increased. Voltage gain of the step-down piezoelectric transformer with respect to input voltage was very stable when the load resistance was in the range of 50-500 $\Omega$ .

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.809-819
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• 2017

In this paper, a new coupled inductor DC-DC converter with a high step-up voltage gain is proposed. It is developed from a clamp-mode coupled-inductor boost converter by incorporating an additional capacitor and diode. The proposed converter is able to achieve the higher voltage gain, while still retaining the switch voltage clamp property of its predecessor. In the paper, operation and analysis of the proposed converter are described. Experimental results from a prototype converter are presented to verify the validity of the analysis. The prototype circuit attains the highest efficiency of 92.8%.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1477-1483
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• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1351-1365
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• 2019

This paper proposes two modified Z-source inverter topologies, namely an embedded L-Z-source inverter (EL-ZSI) and a coupled inductor L-Z source inverter (CL-ZSI). The proposed topologies offer a high voltage gain with a reduced passive component count and reduction in source current ripple when compared to conventional ZSI topologies. Additionally, they prevent overshoot in the dc-link voltage by suppressing heavy inrush currents. This feature reduces the transition time to reach the peak value of the dc-link voltage, and reduces the risk of component failure and overrating due to the inrush current. EL-ZSI and CL-ZSI possess all of the inherent advantages of the conventional L-ZSI topology while eliminating its drawbacks. To verify the effectiveness of the proposed topologies, MATLAB/Simulink models and scaled down laboratory prototypes were constructed. Experiments were performed at a low shoot through duty ratio of 0.1 and a modulation index as high as 0.9 to obtain a peak dc-link voltage of 53 V. This paper demonstrates the superiority of the proposed topologies over conventional ZSI topologies through a detailed comparative analysis. Moreover, experimental results verify that the proposed topologies would be advantageous for renewable energy source applications since they provide voltage gain enhancement, inrush current, dc-link voltage overshoot suppression and a reduction of the peak to peak source current ripple.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.263-271
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• 2013

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in $0.18-{\mu}m$ high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for $1{\mu}F$ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV, $7.5{\mu}A$, and higher than 1 MHz, respectively.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.473-476
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• 2004

AS supply voltage of DRAM is scaled down, voltage circuit that is stable from external noise is more important. $V_{PP}$ voltage is very important, it is biased to gate of memory cell transistor and possible to read and write without voltage down. It has both high pump gain and high power efficiency therefore charge pump circuit is proposed. The circuit is simulated by 0.18${\mu}m$ memory process and 1.2V supply voltage. Compare to CCTS, it is improved 0.43V of pump gain, $3.06\%$ of power efficiency at 6 stage.