• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.653-656
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• 2002

In this paper, we present the simulation results of multi-layer VCO(voltage controlled oscillator), which is composed of resonator, oscillator, and buffer circuit, using EM simulator and nonlinear RF circuit simulator. EM simulator is used for obtaining the EM(Electromagnetic) characteristics of conductor pattern as well as designing the multi-layer VCO. Obtained EM characteristics were used as real components in nonlinear RF circuit simulation. Finally the overall VCO was simulated by the nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was DuPont 951AT, which will be applied for LTCC process. The structure of multi-layer VCO is constructed with 4 conducting layer. Simulated results showed that the output level was about 4.5 [dBm], the phase noise was -104 [dBc/Hz] at 30 [kHz] offset frequency, the harmonics -8 dBc, and the control voltage sensitivity of 30 [MHz/V] with a DC current consumption of 9.5 [mA]. The size of VCO is $6{\times}9{\times}2$ mm(0.11[cc]).

• ETRI Journal
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• v.33 no.5
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• pp.752-758
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• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.4 no.2 s.7
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• pp.81-87
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• 2005

In this paper, a VCDRO(Voltage Control Dielectirc Resonator Oscillator) for signal source of doppler radar system is designed and fabricated. The proposed VCDRO is made with new tuning mechanism using CPW line. The coplanar waveguide of $\lambda_{g}$/2 in length with varactor diode is placed on the metallization side under the dielectric resonator and coupled to it. Tuning varactor diode is mounted at one end of the CPW. The proposed circuit tuned by a CPW allows one more varactor diode to be mounted on the optimized CPW, where a greater sensitivity of frequency tuning is needed. With varying the biasing voltage for the varactor diode from 0 V to 15 V, output frequency tuning of 12 MHz is obtained. The PLDRO exhibits output power of 16.5 dBm with phase noise in the phase locked state characteristic of -115 dBc/Hz at 100 Hz, -105 dBc/Hz at the 10 kHz, and -102 dBc/Hz at 1 Hz offset from 10.525 GHz , respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.3
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• pp.114-123
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• 1998

The multi-resonant converter(MRC) minimizes a parasitic oscillation by using the resonant tank circuit absorbed parasitic reactances existing in a converter circuit. So it si possible that the converter operated at a high frequency has a high efficiency because the losses are reduced. Such a MHz high frequency applications provide a high power density [W/inch3] of the converter. But the resonant voltage stress across a switch of the resonant tank circuit is 4~5 times a input voltage. This h호 voltage stress increases the conduction loss because of on-resistance of a MOSFET with higher rating. Thus, in this paper we proposed the alternated multi-resonant converter (AT MRC) differ from the clamp mode multi-resonant converter and applicated it to the forward MRC. The AT forward MRC can reduce the voltage stress to 2~3 times a input voltage by using two series input capacitor. The control circuit is simple because tow resonant switches are driven directly by the output pulse of the voltage controled oscillator. This circuit type is verified through the experimental converter with 48V input voltage, 5V/50W output voltage/power and PSpice simulation. the measured maximum voltage stress is 170V of 2.9 times the input voltage and the maximum efficiency of 81.66% is measured.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Journal of electromagnetic engineering and science
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• v.10 no.1
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• pp.35-38
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• 2010

A fully integrated parallel-coupled 6-GHz quadrature voltage-controlled oscillator (QVCO) has been designed. The symmetrical parallel-coupled quadrature VCO is implemented using 0.13-${\mu}m$ CMOS process. The measured phase noise is -101.05 dBc/Hz at an offset frequency of 1 MHz. The tuning range of 710 MHz is achieved with a control voltage ranging from 0.3 to 1.4 V. The average output phase error is about $1.26^{\circ}$ including cables and connectors. The QVCO dissipates 10 mA including buffer from the 1.5 V supply voltage. The output characteristic of the differential injection-locked frequency divider (DILFD), which has similar topology to the QVCO, is presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.527-534
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• 1987

Two phase voltage controlled oscillation was realized by using the Electronic analog simulation of nonlinear simultaneous 2st order equation in terms of vibration and it's usefullness was sustined. Sinde it is complex and expensive to implement the circuits actually which composits and multiplicate the two phase signal squared respectively, this paper is obtained the simplificotion and switching circuit. The circuit introducced in this paper had propotionality of frequency to control input voltage, rapid response time, and little phase error, also this circuit operated with very low THD(Total Harmonic Distortion) and constant amplitude at higher than 10 :1 of frequency ratio.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.162-166
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• 2000

본 논문에서는 Ku-band용 전압제어 유전체 공진 발진기를 위상잡음 특성을 고려하여 설계하였다. 유전체의 높은 Q값은 좋은 위상잡음특성에 영향을 주나 전압제어를 위해 바렉터 다이오드의 연결된 튜닝 마이크로스트립라인의 길이에 따라 Q값의 변화하고 이로 인해 위상잡음 특성이 변화하am로 이를 고려하여 최적의 튜닝 마이크로스트립라인 길이를 시뮬레이션 견과를 통해 얻은 후 전압제어 유진체 발진기를 설계 하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.242-245
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• 2001

본 논문은 디지털 위성용 하향변환기에 적용되는 고안정 전압제어 마이크로파 발진기의 위상잡음 특성을 분석하였다. 전압제어 마이크로파 발진기는 능동소자의 비선형 등가모델과 궤환회로의 영향을 고려하여 유전체 공진 마이크로파 발진기를 위상잡음과 출력 전력에 절충(trade-off)하여 설계하였고, 13.25GHz의 발진주파수에서 출력이득은 12dBm이고, 위상잡음은 옵셋 주파수 100KHz 에서 -107.91dBc를 보였다. 바렉터 다이오드 동작에 의한 튜닝 범위는 2MHz/V로 위상동기 발진기에 응용할 수 있음을 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.561-570
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• 2009

Ultra-wideband communication systems based on impulse radio have merits that are possible for the high data rate transmission, high resolution ranging are positioning system. Conventionally, in order to accomplish these features, the high-speed ADC (Analog to Digital Convertor) is necessary to apply radio determination system operating in time domain. However, considering low rate - wireless personal area network (LR-WPAN) aims to low-cost hardware implementation, the expensive ADC converting GHz sampling per second is not appropriate. So, this paper introduces a low complex AR (Auto Regressive) model based non-coherent ranging scheme operating in frequency domain with using low-speed ADC utilizing analog Voltage Control Oscillator (VCO) mode for the frequency domain transformation. To verify the superiority of the proposed ranging and location algorithm working in frequency domain, the suggested IEEE 802.15.4a TG channel model is used to exploit affirmative features of the proposed algorithm with conducting the simulation results.