• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.6
• /
• pp.1-8
• /
• 2000

In this paper, design of sense amplifier for a flash memory minimizing bit line disturbance due to common bit line is presented. There is a disturbance problem at output modes by using common bit line, when the external devices access an internal flash memory. This phenomenon is resulted form hot carrier between floating gates and bit lines by thin oxide thickness. To minimize bit line disturbance, lower it line voltage is required and need sense amplifier to detect data existence in lower bit line voltage. Proposed circuits is operated at lower bit line voltage and we fabricated a embedded flash memory MCU using 0.6u technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.3
• /
• pp.213-216
• /
• 2008

The voltages for pixel electrodes on LCD panels are supplied with analog voltages from LCD Driver ICs (LDIs). The latest LDI developed for large LCD TV's has suffered from the degradation of analog output characteristics (target voltage: AVO and output voltage deviation: dVO). By the failure analysis, humps in $I_D-V_G$ curves have been observed in high voltage (HV) NMOS devices for input transistors in amplifiers. The hump is investigated to be the main cause of the deviation for the driving current in HV NMOS transistors. It also makes the matching between two input transistors worse and consequently aggravates the analog output characteristics. By simply modifying the active layout of HV NMOS transistors, this hump was removed and the analog characteristics (AVO &dVO) were improved significantly. In the help of the improved analog characteristics, it also became possible to reduce the size of the input transistors less than a half of conventional transistors and significantly improve the integration density of LDIs.

• Journal of electromagnetic engineering and science
• /
• v.11 no.1
• /
• pp.27-33
• /
• 2011

In this paper, we propose a high gain, current reused ultra wideband (UWB) low noise amplifier (LNA) that uses TSMC 0.18 ${\mu}m$ CMOS technology. To satisfy the wide input matching and high voltage gain requirements with low power consumption, a resistive current reused technique is utilized in the first stage. A ${\pi}$-type LC network is adopted in the second stage to achieve sufficient gain over the entire frequency band. The proposed UWB LNA has a voltage gain of 12.9~18.1 dB and a noise figure (NF) of 4.05~6.21 dB over the frequency band of interest (1~10 GHz). The total power consumption of the proposed UWB LNA is 10.1 mW from a 1.4 V supply voltage, and the chip area is $0.95{\times}0.9$ mm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.4
• /
• pp.394-402
• /
• 2013

This paper presents design, fabrication and ruggedness test of switching-mode power amplifier using GaN(Gallium Nitride) HEMT(High Electron Mobility Transistor) for S-band radar applications. The power amplifier is designed to Class-F for high efficiency. The input signal for the measurement of the power amplifier is pulse signal at $100{\mu}s$ pulse width and duty cycle of 10 %. The measurement results of the fabricated Class-F power amplifier are a power gain of 10.8 dB, an output power of 40.8 dBm, a power added efficiency(PAE) of 54.2 %, and a drain efficiency of 62.6 %, at the center frequency. We proposed reliability test set-up of a power amplifier for ruggedness test. And we measured output power and efficiency according to VSWR(Voltage Standing Wave Ratio) variation. The designed power amplifier achieved output power of 32.6~41.1 dBm and drain efficiency of 23.4~63 % by changing VSWR, respectively.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.1
• /
• pp.59-67
• /
• 2016

A novel instrumentation amplifier (IA) using fully-differential linear operational transconductance amplifier (FLOTA) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of a FLOTA, two resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into FLOTA converts into two same difference currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the FLOTA and realized the IA used commercial op-amp LF356. Simulation results show that the FLOTA has linearity error of 0.1% and offset current of 2.1uA at input dynamic range ${\pm}3.0V$. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the 60dB was 10MHz. The proposed IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 105mW at supply voltage of ${\pm}5V$.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.48 no.4
• /
• pp.461-466
• /
• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.66 no.8
• /
• pp.1215-1221
• /
• 2017

Parametric array transducers are used for highly directional speaker in an air environments. Piezoelectric micromachined ultrasonic transducers for parametric array transducers need DC-biased voltage driving signals in order to get high-directional quality-sound features. The existing power amplifier such as class A amplifiers has low efficiency and require large volume heatsinks. To overcome the above-mentioned disadvantages of the conventional amplifier, this paper proposes a new power amplifier system. The proposed power amplifier system ensures high linearity of output characteristic by utilizing the push-pull class B type amplifier. Furthermore, the proposed power amplifier system gets high efficiency because it contains the DC-DC converter-type power supply which can perform energy recovery and envelope tracking function. Also the paper suggests the detailed circuit topology. Its characteristics are verified by the detailed experimental results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.8 s.111
• /
• pp.707-712
• /
• 2006

In this paper, dual bias control circuit and PBG(Photonic BandGap) structure have been employed to improve PAE(Power Added Effciency) of the Doherty amplifier on Input power level. The gate and drain bias voltage has been controlled with the envelope of the input RF signal and PBG structure has been employed on the output port of Doherty amplifier. The proposed Doherty amplifier using dual bias controlled circuit and PBG has been improved the average PAE by 8%, $IMD_3$ by -5 dBc. And proposed Doherty amplifier has a high efficiency more than 30% on overall input power level, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.2
• /
• pp.174-180
• /
• 2008

The pulsed amplifier which switches the main supply voltage of RF amplifier according to input pulse signal has good efficiency and low noise level between pulses. And it has simple structure because it doesn't need a pulse modulator at input port. The pulsed amplifier using the conventional switching circuit has slow fall time compared to rise time. We proposed the novel switching circuit for improving the fall time of pulsed amplifier The proposed switching circuit is implemented by replacing FET of conventional circuit with BJT. As a result of appling this circuit to RF pulsed amplifier, the rise and fall time are 5.7 ns and 21.9 ns at 27 dBm output power, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.9
• /
• pp.743-749
• /
• 2002

A 1.5V 70㏈ 100MHz CMOS class-AB complementary operational amplifier is presented. For obtaining the high gain and the high unity gain frequency, the input stage of the amplifier is designed with rail-to-rail complementary differential pairs which are symmetrically parallel-connected with the NMOS and the PMOS differential input pairs, and the output stage is designed to the rail-to-rail class-AB output stage including the elementary shunt stage technique. With this design technique for output stage, the load dependence of the overall open loop gain is improved and the push-pull class-AB current control can be implemented in a simple way. The designed operational amplifier operates perfectly on the complementary mode with 180$^{\circ}$ phase conversion for 1.5V supply voltage, and shows the push-pull class-AB operation. In addition, the amplifier shows the DC open loop gain of 70.4 ㏈ and the unity gain frequency of 102 MHz for $C_{L=10㎊∥}$ $R_{L=1㏁}$ Parallel loads. When the resistive load $R_{L}$ is varied from 1 ㏁ to 1 ㏀, the DC open loop gain of the amplifier decreases by only 2.2 ㏈.a$, the DC open loop gain of the amplifier decreases by only 2.2 dB.