• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.6
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• pp.522-529
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• 2014

This study proposes an isolation amplifier circuit for the sensing and feedback of inverter DC-link voltage, which is inevitable for the precise control of inverter output voltage. The isolation amplifier consists of a pulse-width modulator and a pulse transformer with dual secondary windings. The accuracy of the proposed circuit depends on the precise matching of filter parameters in dual secondary circuits. The influences of parameter inaccuracy on the amplifier performances are analyzed. A modified circuit is proposed to reduce the dependency on filter parameters. The validity of the proposed method is verified through simulation and experiment.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.727-730
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• 2005

In this paper, we propose a new current sense amplifier for low-voltage, high-speed SRAM. As a supply voltage is reduced, a sensing delay is increased owing to reduced cell read current. It causes a low-speed operation in SRAM. To overcome this problem, we present a new current sense amplifier which consists of the current-mirror type circuit with feedback structure. For demonstration, a 0.8-V, 256-Kb SRAM incorporating the proposed current sense amplifier has been designed with $0.18-{\mu}m$ CMOS technology. The simulation results show 15.6ns of the sensing delay reduction in comparison with a previous current sense amplifier and 11.5ns of the sensing delay reduction in comparison with a voltage sense amplifier.

• ETRI Journal
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• v.31 no.3
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• pp.247-253
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• 2009

We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 ${\mu}m$ GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2257-2261
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• 2007

A new CMOS transresistance amplifier for low-voltage analog integrated circuit design applications is presented. The proposed transresistance amplifier circuit based on common-source and negative feedback topology is compared with other recent reported transresistance amplifier. The proposed transresistance amplifier achieves high transresistance gain, gain-bandwidth with the same input/output impedance and the minimum supply voltage $2V_{DSAT}+V_T$. Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS technology was performed and achieved $59dB{\Omega}$ transresistance gain which is above the maximum about $18dB{\Omega}$ compared to transresistance gain of the reported circuit.

• Journal of IKEEE
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• v.20 no.3
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• pp.279-284
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• 2016

This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.364-375
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• 2014

Parametric array transducers are used for long-range and highly directional communication in an underwater environments. The power amplifiers for parametric array transducers should have sufficient linear output characteristic and high efficiency to avoid communication errors, system heating, and fuel problems. But the conventional power amplifier with fixed source voltage is very low efficient due to large power loss by the big difference between the fixed source voltage and the amplifier output voltage. Thus to solve the problems this paper proposes the high efficiency power amplifier for parametric array transducers. The proposed power amplifier ensures high linearity of output characteristic by utilizing the push-pull class B type amplifier and furthermore gets high efficiency by applying the envelope tracking technique that variable source voltage tracks the envelope of the amplified signal. Also the paper suggests the detailed circuit topology and design guideline of class B push-pull type amplifier and variable output voltage AC/DC converter. Its characteristics are verified by the detailed simulation and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.356-359
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• 2006

A monolithic SiGe HBT variable gain driver amplifier(VGDA) with high dB-linear gain control and high linearity has been developed as a driver amplifier with ground-shielded microstrip lines for 5-GHz transmitters. The VGDA consists of three blocks such as the cascode gain-control stage, fixed-gain output stage, and voltage control block. The circuit elements were optimized by using the Agilent Technologies' ADSs. The VGDA was implemented in STMicroelectronics' 0.35${\mu}m$ Si-BiCMOS process. The VGDA exhibits a dynamic gain control range of 34 dB with the control voltage range from 0 to 2.3 V in 5.15-5.35 GHz band. At 5.15 GHz, maximum gain and attenuation are 10.5 dB and -23.6 dB, respectively. The amplifier also produces a 1-dB gain-compression output power of -3 dBm and output third-order intercept point of 7.5 dBm. Input/output voltage standing wave ratios of the VGDA keep low and constant despite change in the gain-control voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.56-62
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• 2002

A new high speed and low voltage swing on-chip BUS using threshold voltage swing driver and dual sense amplifier receiver is proposed. The threshold voltage swing driver reduces the rising time in the bus to 30% of the full CMOS inverter driver and the dual sense amplifier receiver increases twice the throughput. of the conventional reduced-swing buses using sense amplifier receiver. With threshold voltage swing driver and dual sense amplifier receiver combined, approximately 60% speed improvement and 75% power reduction are achieved in the proposed scheme compared to the conventional full CMOS inverter for the on-chip bus.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.53-57
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• 2017

This paper proposes a 401MHz-406MHz low noise amplifier for MedRadio applications. The proposed low noise amplifier adopts a common gate amplifier topology using current reuse gm-boosting technique. The proposed low noise amplifier shows better performance of voltage gain and noise figure than the conventional gm-boosted common gate amplifier in the same power consumption. The proposed current-reuse gm-boosted low noise amplifier achieves a voltage gain of 22 dB, a noise figure of 2.95 dB, and IIP3 of -17 dBm while consuming $170{\mu}W$ from a 0.5 V supply voltage in $0.13{\mu}m$ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.309-315
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• 2010

A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 Hz to 480 Hz, the midband gain programmable from 48.7 dB to 59.5 dB, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 nW in a 0.13 ${\mu}m$ CMOS process at the supply voltage of 0.7 V.