• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.29-36
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• 2008

In this paper, mechanical reliability issues of copper through-wafer interconnections are investigated numerically and experimentally. A hermetic wafer level packaging for MEMS devices is developed. Au-Sn eutectic bonding technology is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of $1mm{\times}1mm{\times}700{\mu}m$. The robustness of the package is confirmed by several reliability tests. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, and copper diffusion phenomenon. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process. After implementing several improvements, reliability tests were performed, and via hole cracking as well as significant changes in the shear strength were not observed. Helium leak testing indicated that the leak rate of the package meets the requirements of MIL-STD-883F specification.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.635-642
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• 2004

The traditional communication protocols such as TCP/IP are not suitable for PC cluster systems because of their high software processing overhead. To eliminate this overhead, industry leaders have defined the Virtual Interface Architecture (VIA). VIA provides two different data transfer mechanisms, a traditional Send/Receive model and the Remote Direct Memory Access (RDMA) model. RDMA is extremely efficient way to reduce software overhead because it can bypass the OS and use the network interface controller (NIC) directly for communication, also bypass the CPU on the remote host. In this paper, we have implemented VIA-based RDMA mechanism in hardware. Compared to the traditional Send/Receive model, the RDMA mechanism improves latency and bandwidth. Our RDMA mechanism can also communicate without using remote CPU cycles. Our experimental results show a minimum latency of 12.5${\mu}\textrm{s}$ and a maximum bandwidth of 95.5MB/s. As a result, our RDMA mechanism allows PC cluster systems to have a high performance communication method.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1724-1725
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• 2011

본 논문에서는 LED 패키지의 방열문제를 해결하기 위해 FR4 PCB에 Via-hole을 형성함으로써 열전달 능력을 향상시키고자 하였다. 또한 FR4 PCB의 면적과 Via-hole 크기 및 수량을 변화를 주어 그에 따른 K-factor를 측정 하였으며 열 저항 특성을 분석하였다. 결과로서, Via-hole을 형성한 FR4 PCB의 경우 초기 면적이 증가함에 따라 열 저항 및 접합온도가 급격히 감소하는 특성을 보였으며 200 [mm2]에서 안정화 되는 특성을 보였다. 또한 PCB 면적 및 Via-hole을 형성함에 따라 광 출력이 최대 17% 향상 되었다. 따라서 접합온도 및 열 저항에 있어서 PCB면적의 증가 및 Via-hole을 구성함에 있어 열전달 능력을 향상시킬 수 있음을 확인하였다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.12
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• pp.57-63
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• 2010

The efficiency of LED package is increasing by applying the high power, and a existing lighting is changing as the LED lighting. However, many problems have appeared by heat. Therefore, in order to solve thermal problems, LED lighting is designing in several ways, but the advantages of LED lighting is fading due to increase the prices and volumes. In this study, we try to improve the thermal performance by formation of via holes. The junction temperature and thermal resistance in the FR4-PCB with via-holes of 0.6[mm] was excellent in experiment and FR4-PCB with Via-holes of 0.6[mm] was excellent in simulation without solder. Further, the thermal resistance and the optical properties can be improved through a formation of via-holes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.329-332
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• 2011

최근 사용하는 정보량의 증가로 인해 디지털 회로가 점점 고속, 소형 집적화를 요구로 인해 인쇄회로 기판 역시 높은 신뢰성과 소형화가 요구되어 지고 있다. 특히 POWER PLAN / GROUND PLAN 간 임피던스 영향, 주파수 영향을 고려하여 GROUND / POWER VIA를 통해 개선하고 있으나 너무 많은 VIA가 사용되어 PCB 제조업체 입장에서는 단가 상승 및 납기 지연, 불량요인이 지속적으로 증가하고 있다. 하여 본 논문에서는 VIA 개체수 최적화를 검증 하기 위하여 정형화된 PCB구조의 기본 Design을 활용하여 POWER PLAN과 GROUND PLAN 사이에 VIA의 특정 개수에서 IMPEDANCE값이 수렴하는 것을 검증하여 최적화된 VIA개수를 찾아 보았다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2008.11a
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• pp.21-22
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• 2008

$SF_6/O_2$ 플라즈마 에칭을 통한 반도체 칩의 3차원 집적에 응용되는 through-silicon-via (TSV) 구조형성 연구를 수행하였다. Si via 형상은 $SF_6$, $O_2$의 가스 비율과 에칭이 되는 Silicon 기판의 온도에 의존함을 알수 있었다. 또한 Si via 형상에서 최소의 언더컷 (undercut) 과 측벽에칭 (local bowing) 은 black Si이 나타나는 공정조건에서 나타남을 확인하였다. 더 나아가 저온을 이용한 via 형성시 via 측벽에 형성되는 passivation layer와 mask의 성질이 저온으로 인해 high-aspect-ratio를 갖는 via를 형성할 수 있음을 알 수 있었다.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.429-429
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• 2006

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.3-17
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• 2003

.Package Trend -> Memory : Lighter, Thinner, Smaller & High Density => SiP, 3D Stack -> MPU : High Pin Counts & Multi-functional => FCBGA .Interposer Trend -> Via - Unfilled Via => Filled Via - Staggered Via => Stacked Via -> Emergence of All-layer Build-up Processes -> Interposer Material Requirement => Low CTE, Low $D_{k}$, Low $D_{f}$, Halogen-free .New Technology Concept -> Embedded Passives, Imprint, MLTS, BBUL etc.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.695-698
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• 2010

본 논문은 High-speed signal에 대한 기본적인 설계 방법론, Differential signaling, Impedence matching, Decoupling Method 등에 대하여 논한 후 High-speed signal 의 전송 품질을 개선하기 위한 GND via 의 효과에 대하여 논하고자 한다. S-parameter simulation 및 실제 제품 적용 후 파형의 변화를 관찰하여 GND via 의 효용성을 살펴보아 High-speed signal Design 할 때 Design limitation 상황에 대해 적절한 방법론을 말하고자 한다.