• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.79-85
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• 2005

In this paper, low-power design and implementation techniques for IMT-2000 interpolation filter are proposed. Processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized for low-power implementation. proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of filter coefficient. Finally, in third shift register block, multiplied values are output and stored in shift register. For IMT-2000 interpolation filter, proposed and conventional structures are implemented by using Verilog-HDL coding. Gate counts for the proposed structure is reduced to 31.57% comparison with those of the conventional one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.137-141
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• 2007

This paper proposes a cost-effective architecture design of an angle-of-arrival (AOA) estimator based on the multiple signal identification and classification (MUSIC) algerian in UWB systems adapting Multi-band OFDM (MB-OFDM) techniques with two-receive antennas. In the proposed method, by modifying the equations of algorithm in order to remove the high computational functions, the computation power can be significantly reduced without significant performance degradation. The proposed architecture is designed and verified by Verilog HDL, and implemented into 0.13um CMOS standard cell and Xilinx FPGA circuits for the estimation of hardware complexity and computation power. From the results of the implementations, we can find that the proposed circuits reduces the hardware complexity by about 43% and the estimated computation power by about 23%, respectively, compared to the architecture employing the original MUSIC algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.77-82
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• 2008

H.264 is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. It has different architecture depending on demands since it is a lied from small image of QVGA to large size of HD. In this paper, We propose a scalable architecture for intra-prediction of H.264 decoders. The proposed scheme has a scalable architecture that can accommodate up to 4 processing elements depending on performance demands and can reduce the number of access to memory using efficient memory management so as to be energy-efficient. We design the intra-prediction unit using Verilog-HDL and verily it by prototyping using an FPGA. The performance is analyzed using the results of design.

• Journal of IKEEE
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• v.13 no.4
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• pp.110-115
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• 2009

The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation. The quarter-pixel interpolation is achieved using 6-tap horizontal or vertical FIR filters for luminance data and bilinear FIR filters for chroma data. We propose the architecture for interpolation of luminance and chroma data in H.264 decoders. It is composed of dual-channel pipelined processing elements and can interpolate integer-, half- and quarter-pixel data. The number of the processing cycles is different depending on the position. The processing elements are composed of adders and shifters to reduce the complexity while the accuracy of the pixel data are maintained. We design interpolators for luminance and chroma data using Verilog-HDL and verify the function and performance by implementing using an FPGA.

• Journal of Advanced Navigation Technology
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• v.21 no.4
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• pp.386-393
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• 2017

Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.4
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• pp.321-328
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• 2008

In this paper, we propose the hardware architecture of two-dimensional discrete wavelet transform (2D DWT) and quantization for using JPEG2000. Color 2-D DWT processor is proposed that is to apply to JPEG 2000 Hard-wired Encoder. JPEG 2000 DWT processor uses the Daubechies' (9,7) bi-orthogonal filter, and we design by minimizing error of the DWT transformer by ${\pm}1$ LSB during compression and decompression. We designed the DWT filters that using by using shift and adder structure instead of multiplier structure which raise the hardware complexity. It is improve the operation speed of filters and reduce the hardware complexity. The proposed system is designed by the hardware description language Verilog-HDL and verified by Synopsys Design Analyzer using TSMC 0.25${\mu}m$ ASIC library.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.68-75
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• 2011

The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.

• Journal of Advanced Navigation Technology
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• v.19 no.6
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• pp.544-551
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• 2015

In this paper, the design and implementation results of the optical flow estimator (OFE) for moving object detection (MOD) in advanced driver assistance system (ADAS). In the proposed design, Brox's algorithm with global optimization is considered, which shows the high performance in the vehicle environment. In addition, Cholesky factorization is applied to solve Euler-Lagrange equation in Brox's algorithm. Also, shift register bank is incorporated to reduce memory access rate. The proposed optical flow estimator was designed with Verilog-HDL, and FPGA board was used for the real-time verification. Implementation results show that the proposed optical flow estimator includes the logic slices of 40.4K, 155 DSP48s, and block memory of 11,290Kbits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.