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Development and Verification of SoC Platform based on OpenRISC Processor and WISHBONE Bus  

Bin, Young-Hoon (Graduate School of Information and Communication, Hanbat National University)
Ryoo, Kwang-Ki (Graduate School of Information and Communication, Hanbat National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.1, 2009 , pp. 76-84 More about this Journal
Abstract
This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.
Keywords
SoC 플랫폼;IP 개발 및 검증;온 칩 버스;임베디드 프로세서;
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