Journal of Advanced Navigation Technology (한국항행학회논문지)

The Korean Navigation Institute (한국항행학회)
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Design and Implementation of Optical Flow Estimator for Moving Object Detection in Advanced Driver Assistance System

첨단운전자보조시스템용 이동객체검출을 위한 광학흐름추정기의 설계 및 구현

  • Yoon, Kyung-Han (School of Electronics and Information Engineering, Korea Aerospace University) ;
  • Jung, Yong-Chul (School of Electronics and Information Engineering, Korea Aerospace University) ;
  • Cho, Jae-Chan (School of Electronics and Information Engineering, Korea Aerospace University) ;
  • Jung, Yunho (School of Electronics and Information Engineering, Korea Aerospace University)
  • 윤경한 (한국항공대학교 항공전자정보공학부) ;
  • 정용철 (한국항공대학교 항공전자정보공학부) ;
  • 조재찬 (한국항공대학교 항공전자정보공학부) ;
  • 정윤호 (한국항공대학교 항공전자정보공학부)
  • Received : 2015.12.03
  • Accepted : 2015.12.12
  • Published : 2015.12.30
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Abstract

In this paper, the design and implementation results of the optical flow estimator (OFE) for moving object detection (MOD) in advanced driver assistance system (ADAS). In the proposed design, Brox's algorithm with global optimization is considered, which shows the high performance in the vehicle environment. In addition, Cholesky factorization is applied to solve Euler-Lagrange equation in Brox's algorithm. Also, shift register bank is incorporated to reduce memory access rate. The proposed optical flow estimator was designed with Verilog-HDL, and FPGA board was used for the real-time verification. Implementation results show that the proposed optical flow estimator includes the logic slices of 40.4K, 155 DSP48s, and block memory of 11,290Kbits.

본 논문에서는 첨단 운전자 보조 시스템 (ADAS; advanced driver assistance system) 용 이동객체검출 (MOD; moving object detection)을 위한 광학흐름추정기 (OFE; optical flow estimator) 의 하드웨어 구조 설계 결과를 제시하였다. 광학흐름추정 알고리즘은 차량 환경에서 높은 정확도를 나타내는 광역 최적화 (global optimization) 기반 Brox 알고리즘을 적용하였다. Brox 알고리즘의 에너지 범함수 (energy functional)를 최소화 하는 과정에서 생성되는 Euler-Lagrange 방정식을 풀기 위해 하드웨어 구현에 용이한 Cholesky factorization이 적용되었으며, 메모리 접근율 (memory access rate)를 줄이기 위해 시프트 레지스터 뱅크 (shift register bank)를 도입하였다. 하드웨어 구현은 Verilog-HDL을 사용하였으며, FPGA 기반 설계 및 검증이 수행되었다. 제안된 광학흐름추정기는 40.4K개의 logic slice 및 155개의 DSP48s, 11,290 Kbit의 block memory로 구현되었다.

Keywords

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