• Title/Summary/Keyword: verilog HDL

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Digital Correlator Design for GPS/GLONASS Receiver (GPS/GLONASS 수신기용 디지털 상관기 설계)

  • 조득재;최일홍;박찬식;이상정
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.275-275
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    • 2000
  • This paper designs a digital correlator for the integrated GPS/GLONASS receiver consisting of DCO, carrier cycle counter, code generator, code phase counter, mixer, epoch counter, accumulator. It is designed using Verilog-HDL(Verilog-Hardware Description Language) and synthesized using EDA(Electronic Design Automation) tools. The performance of the designed digital correlator is verified by the functional simulation and real satellite tracking experiments.

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Design of Robort using VHDL and Verilog (VHDL과 Verilog를 이용한 FPGA 로봇설계)

  • Jin, Hyun-Soo;Chae, Gyu-Soo
    • Proceedings of the KAIS Fall Conference
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    • 2010.05a
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    • pp.360-362
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    • 2010
  • 본 논문에서는 SoC 키트에 해당하는 iRoV-Lab 3000의 장착된 로봇 모듈인 FPA 모듈, Stepper Motor 모듈, 적외선 송수신 센서 모듈, 카메라 모듈, RF 모듈 LED, TEXT LCD, 7-segment를 제어하기 위한 FPGA를 사용하며, FPGA설계를 위해 Schematic Design 또는 HDL에 대해 연구한다. FPGA의 내부구조를 이해하고 개발환경을 구축할 수 있다. 로봇의 구성요소와 각각의 구성요소(Sensor 모듈, display 모듈, Stepper Motor 모듈, RF 모듈)의 동작 원리를 개발한다.

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A VLSI Architecture Design of CDMA/TDMA Modem Chipsets for Wireless Telemetry Systems (CDMA/TDMA 기반 무선 원격계측 시스템용 모뎀의 VLSI 구조 설계)

  • 이원재;이성주;이서구;정석호;김재석
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.5
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    • pp.107-114
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    • 2004
  • In this paper, we present the architecture design of CDMA/TDMA modem chipset for wireless telemetry system. The wireless telemetry system a measuring data collecting system from many RTs(Remote Terminal) installed at the specific area using wireless communication technology. It consists of CU single CU (Central Unit) for collecting data and a large amount of RTs for transmitting the measuring data. We propose the hardware architecture of the modem for RT and CU. We also design those modem using Verilog HDL and synthesis them using Synopsys$^{TM}$ CAD tool. The modem of RT is implemented with 27K gates and that of CU is implemented around 220k gates using 0.6${\mu}{\textrm}{m}$ CMOS standard cell. The proposed system is implemented and tested using Altera$^{TM}$ FPGA.PGA.

Implementation of FlexRay Systems for Vehicle Appliacations (차량 내 통신을 위한 FlexRay 시스템 구현)

  • Jeon, Chang-Ha;Lee, Jae-Kyung;Jang, In-Gul;Chung, Jin-Gyun
    • Proceedings of the IEEK Conference
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    • 2009.05a
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    • pp.182-184
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    • 2009
  • FlexRay is a new standard of network communication system which provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for future automotive and ship applications. FlexRay communication controller(CC) is the core of the FlexRay protocol specification. In this paper, we first design the FlexRay CC protocol specification and function parts using SDL(Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay CC system was synthesized using Samsung $0.35{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 80 MHz. In addition, to show the validity of the designed FlexRay system, the FlexRay system is combined with sound source localization system in Robot applications. The combined system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

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Low-power Radix-4 FFT Structure for OFDM using Distributed Arithmetic (Distributed Arithmetic을 사용한 OFDM용 저전력 Radix-4 FFT 구조)

  • Jang Young-Beom;Lee Won-Sang;Kim Do-Han;Kim Bee-Chul;Hur Eun-Sung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.43 no.1 s.307
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    • pp.101-108
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    • 2006
  • In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show $61.02\%$ cell area reduction comparison with those of the conventional multiplier butterfly structure. furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show $46.1\%$ cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

Design of Security-Enhanced RFID Authentication Protocol Based on AES Cipher Algorithm (AES 암호 알고리듬 기반 보안성이 강화된 RFID 인증 프로토콜 설계)

  • Kang, Min-Sup
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.12 no.6
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    • pp.83-89
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    • 2012
  • This paper proposes the design of a security-enhanced RFID authentication protocol which meets the privacy protection for tag bearers. The protocol which uses AES(Advanced Encryption Standard) cipher algorithm is based on a three-way challenge response authentication scheme. In addition, three different types of protocol packet formats are also presented by extending the ISO/IEC 18000-3 standard for realizing the security-enhanced authentication mechanism in RFID system environment. Through the comparison of security, it was shown that the proposed scheme has better performance in user data confidentiality, Man-in-the-middle replay attack, and replay attack, and forgery resistance, compared with conventional some protocols. In order to validate the proposed protocol, a digital Codec of RFID tag is also designed based on the protocol. This Codec has been described in Verilog HDL and also synthesized using Xilinx Virtex XCV400E device.

Study of Optimization for High Performance Adders (고성능 가산기의 최적화 연구)

  • 허석원;김문경;이용주;이용석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.5A
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    • pp.554-565
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    • 2004
  • In this paper, we implement single cycle and multi cycle adders. We can compare area and time by using the implemented adders. The size of adders is 64, 128, 256-bits. The architecture of hybrid adders is that the carry-out of small adder groups can be interconnected by utilizing n carry propagate unit. The size of small adder groups is selected in three formats - 4, 8, 16-bits. These adders were implemented with Verilog HDL with top-down methodology, and they were verified by behavioral model. The verified models were synthesized with a Samsung 0,35(um), 3.3(V) CMOS standard cell library while a using Synopsys Design Compiler. All adders were synthesized with group or ungroup. The optimized adder for a Crypto-processor included Smart Card IC is that a 64-bit RCA based on 16-bit CLA. All small adder groups in this optimized adder were synthesized with group. This adder can operate at a clock speed of 198 MHz and has about 961 gates. All adders can execute operations in this won case conditions of 2.7 V, 85 $^{\circ}C$.

Three-phase 3-level and 2-level SVPWM Implementation with 100 kHz Switching Frequency using FPGA (FPGA를 이용한 100 kHz 스위칭 주파수의 3상 3-level과 2-level의 SVPWM의 구현)

  • Moon, Kyeong-Rok;Lee, Dong-Myung
    • Journal of IKEEE
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    • v.24 no.1
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    • pp.19-24
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    • 2020
  • This paper presents a 3-level, 2-level SVPWM technique with 100 kHz switching using Verilog HDL, one of the languages of FPGA. In the case of IGBT devices mainly used in inverters, they have a switching frequency around 20kHz. Recent research and development of next-generation power semiconductor devices such as GAN has enabled switching of more than 100kHz, which can miniaturize power converters, and apply various new algorithms due to the injection of harmonics. In the existing system using the IGBT, the control using the DSP is common, but the controller configuration for 100 kHz switching requires the use of FPGA. Therefore, this paper explains the theory and implementation of SVPWM applied to two-level and three-level inverters using FPGAs and verifies the performance through the output waveform. In addition, this paper implements 3-level SVPWM by using only one carrier instead of using two carriers in the conventional method.

Implementation of FlexRay Communication Controller Protocol and its Application to a Robot System (FlexRay 프로토콜 설계 및 로봇 시스템 응용)

  • Kang, Hyun-Soo;Xu, Yi-Nan;Kim, Yong-Eun;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.6
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    • pp.1-7
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    • 2008
  • FlexRay is a new standard of network communication system which provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for future automotive applications. FlexRay communication controller (CC) is the core of the FlexRay protocol specification. In this paper, we first design the FlexRay CC protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay CC system was synthesized using Samsung $0.35\;{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 80 MHz. In addition, to show the validity of the designed FlexRay system the FlexRay system is combined with sound source localization system in Robot applications. The combined system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

Implementation of FlexRay Protocol Specification and its Application to a Automobile Advance Alarm System (FlexRay 프로토콜 설계 및 자동차 경보 시스템 응용)

  • Xu, Yi-Nan;Yang, Sang-Hoon;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.8
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    • pp.98-105
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    • 2008
  • FlexRay is a high-speed communications protocol with high flexibility and reliability. It was devised by automotive manufacturers and semiconductor vendors and implemented as on vehicle LAN protocol using x-by-wire systems. FlexRay provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for automotive applications. In this paper, we first design the FlexRay communication controller, bus guardian protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay system was synthesized using Samsung $0.35{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 76 MHz. In addition, to show the validity of the designed FlexRay system, the FlexRay system is combined with automobile advance alarm system in vehicle applications. The FlexRay system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.