• Journal of Electrical Engineering and Technology
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• v.12 no.1
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• pp.189-197
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• 2017

This paper elaborates two novel proposed topologies (type-I and type-II) of the high step-up DC-DC converter using switched inductor and voltage multiplier cell. The advantages of these proposed topologies are the less voltage stress on semiconductor devices, low device count, high power conversion efficiency, high switch utilization factor and high diode utilization factor. We analyze the Type-II topologies operating principle and mathematical analysis in detail in continuous conduction mode. High-intensity discharge lamp for the automotive application can use the derived topologies. The proposed converters give better performance when compared to the existing types. Also, it is found that the proposed type-II converter has relatively higher voltage gain compared to the type-I converter. A 40 W, 12 V input voltage and 72 V output voltage has developed for the type-II converter and the performances are validated.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.234-237
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• 2008

This paper deals with a new single-phase Z-source matrix converter (SZMC) topology. Unlike other conventional configurations, the proposed SZMC is not only a step-up frequency converter but also a step-down frequency converter and a voltage boost capability. Thus, the proposed SZMC is also called a frequency step-up/down and voltage step-up converter. A safe-commutation strategy is used in SZMC as free-wheeling operation to eliminate voltage spikes on switches. The operating principles and experimental results of the proposed SZMC are presented.

• Journal of IKEEE
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• v.12 no.1
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• pp.34-42
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• 2008

This paper proposes a new on-chip voltage down converter(VDC), which employs a new reference voltage generator(RVG). The converter adopts a temperature-independence reference voltage generator, and a voltage-up converter. The architecture of the proposed VDC has a high-precision, and it was verified based on a 0.25${\mu}m$ 1P5M standard CMOS technology. For 2.5V to 1.0V conversion, the RVG circuit has a good characteristics such as temperature dependency of only 0.2mV/$^{\circ}C$, and the voltage-up circuit has a good voltage deviation within ${\pm}$0.12% for ${\pm}$5% variation of supply voltage VDD. The output voltage is stabilized with ${\pm}$1mV for load current varying from 0 to 100mA.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.501-506
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• 2013

A hold-up time compensation circuit is proposed to get high efficiency of the front-end phase-shifted full bridge DC/DC converter. The proposed circuit can make the phase-shifted full bridge front-end DC/DC converter built with 0.5 duty ratio so that the conduction loss of the primary side and voltage stress across rectifier in the secondary side are reduced and the higher efficiency can be obtained. Furthermore, the requirement of an output filter significantly can diminish due to the perfect filtered waveform. A 12V/100A prototype has been made and experimental results are given to verify the theoretic analysis and detailed features.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.77-79
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• 1999

In this paper, designed scheme and the performance results of implemented Grand alliance DTV RF up-converter are described. It can generate all channel band (ch.2-ch.60) of Korean broadcasting channel band. The experiment result shows the implemented RF up-converter satisfy the ATSC standards.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.443-444
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• 2008

A double-balanced frequency up-converter using the Gilbert cell structure has been designed with the TSMC $0.18\;{\mu}m$ CMOS library. The frequency up-converter consists of a Mixer core and IF / LO balun. Frequency Up-converter exhibits a 3.4 dB conversion gain with a - 7.6 dBm $P_{1dB}$ for IF power of -10 dBm and LO power of 0 dBm inputs. It also exhibits 92.2 % modulation depth as a ASK modulator.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.346-349
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• 2003

A SiGe HBT MMIC double balaced up-converter has been designed and fabricated for C-band WLAN applications. The up-converter is based on the Gilbert cell mixer with an active baluns for differential inputs of LO and IF signals. The designed up-converter exhibits a conversion gain 12.5dB for a -10 dBm LO power. It also exhibits LO-RF isolation of 19.3dBc, and IF-RF isolation of 23.3 dBc at a 1-dB compression point of -14.2dBm

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.273-276
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• 2003

In this paper, we designed and made up/down converter (UDC) for using W-CDMA digital pre-distortion system which is one of the efficiency enhancement techniques. UDC is required that frequency up(baseband to RF) and down(RF to baseband) of information signals. The focus of the design and PCB layout is to satisfy the linearity of the UDC. We tested that UDC was satisfied specification which is based on 3GPP base stations and repeaters. The ACLR results which are -51.84dBc(Up Converter) and -55.0dBc(Down Converter) at upper 5 MHz offset from center-frequency show that UDC satisfy the 3GPP specification with superior linearity data.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1069-1073
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• 2019

In this paper, an alternative non-isolated DC-DC converter with a high voltage boosting capability is proposed. Two inductors are used and one of them has its flux linkage increases during its charging period to achieve a high step-up voltage gain. Among the three integrated capacitors, one portrays the partial characteristic of the switched-capacitor technique, while the other two are connected in series across the load. With the two switches controlled using the same duty cycle, the proposed topology demonstrates the merits of a higher and wider range of step-up voltage gain when compared with recent topologies. In addition, a reduction in loss is induced and a higher efficiency is ensured with all the voltage stresses constrained within the output voltage. Operation of the proposed converter is analyzed and validated through experimental results obtained with a prototype.

• Journal of Electrical Engineering and Technology
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• v.10 no.6
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• pp.2297-2306
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• 2015

This paper presents the development of a system with a reverse matrix converter (RMC) for permanent magnet synchronous motor (PMSM) drive and its effective control method. The voltage transfer ratio of the general matrix converter is restricted to a maximum value of 0.866, which is not suitable for applications whose source voltages are lower than the load voltages. The proposed RMC topology can step up the voltage without any additional components in the conventional circuit. Its control method is different from traditional matrix converter’s one, thus this paper proposes control schemes of RMC by means of controlling both the generator and motor side currents with properly designed control loop. The converter can have sinusoidal input/output current waveforms in steady state condition as well as a boosted voltage. In this paper, a hardware system with an RMC for a PMSM drive system is described. The performance of the system was investigated through experiments