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http://dx.doi.org/10.6113/TKPE.2013.18.5.501

Phase-Shifted Full Bridge(PSFB) DC/DC Converter with a Hold-up Time Compensation Circuit for Information Technology (IT) Devices  

Yi, Kang-Hyun (School of Electronic and Electric Eng., Daegu University)
Publication Information
The Transactions of the Korean Institute of Power Electronics / v.18, no.5, 2013 , pp. 501-506 More about this Journal
Abstract
A hold-up time compensation circuit is proposed to get high efficiency of the front-end phase-shifted full bridge DC/DC converter. The proposed circuit can make the phase-shifted full bridge front-end DC/DC converter built with 0.5 duty ratio so that the conduction loss of the primary side and voltage stress across rectifier in the secondary side are reduced and the higher efficiency can be obtained. Furthermore, the requirement of an output filter significantly can diminish due to the perfect filtered waveform. A 12V/100A prototype has been made and experimental results are given to verify the theoretic analysis and detailed features.
Keywords
hold up time; efficiency; PSFB(phase-shifted full bridge) converter; front-end DC/DC converter;
Citations & Related Records
Times Cited By KSCI : 4  (Citation Analysis)
연도 인용수 순위
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