• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.943-946
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• 1999

In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given path-length skew bound. The algorithm onstructs a bounded-skew tree(BST) in two steps:(ⅰ) a bottom-up phase to construct a binary tree of shortest-distance feasible regions which represent the loci of possible placements of clock entry points, and (ⅱ) a top-down phase to determine the exact locations of clock entry points. Experimental results show that our clock routing algorithm, named BST/DME, can produce a set of solutions with skew and wirelength trade-off.

• Journal of Sensor Science and Technology
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• v.28 no.4
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• pp.240-245
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• 2019

Phase interpolation is widely adopted in frequency synthesizers and clock-and-data recovery systems to produce an intermediate phase from two existing phases. The intermediate phase is typically generated by combining two input phases with different weights. Unfortunately, this results in non-uniform phase steps. Alternatively, the intermediate phase can be generated by successive approximation, where the interpolated phase at each approximation stage is obtained using the same weight for the two intermediate phases. As a proof of concept, this study presents a 2-GHz 8-bit successive approximation digital-to-phase converter that is designed using 65-nm CMOS technology. The converter receives an 8-phase clock signal as input, and the most significant bit (MSB) section selects four phases to create two sinusoidal waveforms using a harmonic rejection filter. The remaining least significant bit (LSB) section applies the successive approximation to generate the required intermediate phase. Monte-Carlo simulations show that the proposed converter exhibits 0.46-LSB integral nonlinearity and 0.31-LSB differential nonlinearity with a power consumption of 3.12 mW from a 1.2-V supply voltage.

• Animal cells and systems
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• v.9 no.3
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• pp.153-160
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• 2005

Most living organisms exhibit the circadian rhythm in their physiology and behavior. Recent identification of several clock genes in mammals has led to the molecular understanding of how these components generate and maintain the circadian rhythm. Many reports have implicated the photic induction of either mPer1 or mPer2 in the hypothalamic region called the suprachiasmatic nucleus (SCN) to phase shift the brain clock. It is now established that peripheral tissues other than the brain also express these clock genes and that the clock machinery in these tissues work in a similar way to the SCN clock. To determine the role of the two canonical clock genes, mPer1 and mPer2, in the peripheral clock shift, stable HEK293EcR cell lines that can be induced and stably express these proteins were prepared. By regulating the expression of these proteins, it could be shown that induction of the clock genes, either mPer1 or mPer2 alone is not sufficient to cause clock phase shifting in these cells. Our real-time PCR analysis on these cells indicates that the induction of mPER proteins dampens the expression of the clock-specific transcription factor mBmal1. Altogether, our present data suggest that mPer1 and mPer2 may not function in clock shift or take part in differential roles on the peripheral circadian clock.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.188-193
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• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.8-12
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• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.7
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• pp.624-628
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• 2008

This paper is concerned with multiple motor control using a distributed network control method. Speed and position of multiple motors are synchronized using clock synchronized distributed controllers. CAN (controller area network) is used and a new clock synchronization algorithm is proposed and implemented. To verify the proposed control algorithm, two disks which are attached on two motor shafts are controlled to rotate at the same speed and phase angle with the same time base using network clocks.

• ETRI Journal
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• v.36 no.2
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• pp.321-324
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• 2014

This letter describes a two-phase clock oxide thin-film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART-SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from -4 V to 5 V at a line time of $5{\mu}s$. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively -12.6 dB and -26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16-stage shift registers at $V_{TH}=-1.56V$, compared to 11.5 mW for the conventional circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.594-600
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• 2015

A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from $0^{\circ}$ to $360^{\circ}$ with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies $0.047mm^2$. The $jitter_{rms}$ and $jitter_{pk-pk}$ of the output clock are 1.91 ps and 18 ps, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.2
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• pp.193-197
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• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.1-8
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• 2004

A novol clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. This scheme has ideal zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit. For analyzing suitable line structures to FCLs, microstrip line and coplanar line are placed with folded clock lines. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than lops at 1㎓ and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1㎓. Also the results show that the minimum skews of clock signals regardless of process, voltage, and temperature variation are invariant.